A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.
Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A chip comprising: a silicon substrate; a first internal circuit in or on said silicon substrate; a second internal circuit in or on said silicon substrate; a dielectric layer over said silicon substrate; a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to said first internal circuit; a second interconnecting structure over said silicon substrate and in said dielectric layer, wherein said second interconnecting structure is connected to said second internal circuit; a passivation layer over said dielectric layer, wherein said passivation layer comprises a nitride, wherein one of multiple openings in said passivation layer has a diameter between 0.5 and 30 micrometers; a first via in one of said multiple openings, wherein said first via is connected to said first interconnecting structure; a second via in one of said multiple openings, wherein said second via is connected to said second interconnecting structure; and a clock bus over said passivation layer, wherein said clock bus is connected to said first and second vias, wherein said first internal circuit is connected to said second internal circuit through, in sequence, said first interconnecting structure, said first via, said clock bus, said second via and said second interconnecting structure.
A chip includes a silicon substrate with first and second internal circuits. A dielectric layer covers the substrate. First and second interconnect structures reside within this dielectric layer, connecting to the respective internal circuits. A passivation layer (made of nitride) sits above the dielectric layer, featuring openings (0.5-30 micrometers). First and second vias fill these openings, linking to the interconnect structures. A clock bus lies above the passivation layer, connecting to both vias, thus enabling communication between the first and second internal circuits in the path: first interconnect -> first via -> clock bus -> second via -> second interconnect.
2. The chip of claim 1 further comprising a third internal circuit in or on said silicon substrate, wherein said first interconnecting structure is connected to said third internal circuit, wherein said first internal circuit is connected to said third internal circuit through said first interconnecting structure, wherein said third internal circuit is connected to said second internal circuit through, in sequence, said first interconnecting structure, said first via, said clock bus, said second via and said second interconnecting structure.
The chip described previously (a silicon substrate with first and second internal circuits connected by interconnects, vias, and a clock bus over a passivation layer) also includes a third internal circuit on the silicon substrate. The first interconnect structure connects to the third internal circuit. The first and third circuits communicate via the first interconnect. The third circuit communicates with the second circuit through the same path as before: first interconnect -> first via -> clock bus -> second via -> second interconnect.
3. The chip of claim 2 further comprising a fourth internal circuit in or on said silicon substrate, wherein said second interconnecting structure is connected to said fourth internal circuit, wherein said second internal circuit is connected to said fourth internal circuit through said second interconnecting structure, wherein said first internal circuit is connected to said fourth internal circuit through, in sequence, said first interconnecting structure, said first via, said clock bus, said second via and said second interconnecting structure, and wherein said third internal circuit is connected to said fourth internal circuit through, in sequence, said first interconnecting structure, said first via, said clock bus, said second via and said second interconnecting structure.
The chip described previously (a silicon substrate with first, second, and third internal circuits connected by interconnects, vias, and a clock bus over a passivation layer) also includes a fourth internal circuit on the silicon substrate. The second interconnect connects to this fourth circuit. The second and fourth circuits communicate via the second interconnect. Now, the first and fourth circuits communicate in sequence via the path: first interconnect -> first via -> clock bus -> second via -> second interconnect. Also, the third and fourth circuits communicate via the same path: first interconnect -> first via -> clock bus -> second via -> second interconnect.
4. The chip of claim 2 further comprising a fourth internal circuit in or on said silicon substrate, wherein said first interconnecting structure is connected to said fourth internal circuit, wherein said first internal circuit is connected to said fourth internal circuit through said first interconnecting structure, wherein said third internal circuit is connected to said fourth internal circuit through said first interconnecting structure, wherein said fourth internal circuit is connected to said second internal circuit through, in sequence, said first interconnecting structure, said first via, said clock bus, said second via and said second interconnecting structure.
The chip described previously (a silicon substrate with first, second, and third internal circuits connected by interconnects, vias, and a clock bus over a passivation layer) further includes a fourth internal circuit on the silicon substrate. The first interconnect connects to the fourth circuit. The first and fourth circuits communicate via the first interconnect. The third and fourth circuits communicate through the first interconnect as well. Finally, the fourth circuit connects to the second circuit in the path: first interconnect -> first via -> clock bus -> second via -> second interconnect.
5. The chip of claim 1 further comprising a driver, receiver or I/O circuit in or on said silicon substrate, a third interconnecting structure over said silicon substrate and in said dielectric layer, wherein said third interconnecting structure is connected to a first terminal of said driver, receiver or I/O circuit, and a third via in one of said multiple openings, wherein said third via is connected to said third interconnecting structure and to said clock bus, wherein said first terminal is connected to said first internal circuit through, in sequence, said third interconnecting structure, said third via, said clock bus, said first via and said first interconnecting structure, and wherein said first terminal is connected to said second internal circuit through, in sequence, said third interconnecting structure, said third via, said clock bus, said second via and said second interconnecting structure.
The chip described previously (a silicon substrate with first and second internal circuits connected by interconnects, vias, and a clock bus over a passivation layer) also includes a driver, receiver, or I/O circuit on the silicon substrate. A third interconnect resides in the dielectric layer, connected to a first terminal of this driver/receiver/I/O circuit. A third via exists in the passivation layer connecting the third interconnect to the clock bus. The first terminal connects to the first internal circuit through the following path: third interconnect -> third via -> clock bus -> first via -> first interconnect. It also connects to the second internal circuit via the path: third interconnect -> third via -> clock bus -> second via -> second interconnect.
6. The chip of claim 5 further comprising an ESD circuit in or on said silicon substrate and a fourth interconnecting structure over said silicon substrate and in said dielectric layer, wherein said ESD circuit is connected to a second terminal of said driver, receiver or I/O circuit through said fourth interconnecting structure.
The chip described previously (including driver/receiver/I/O and interconnects, vias, clock bus) also includes an ESD (electrostatic discharge) circuit located on the silicon substrate. A fourth interconnect, also located in the dielectric layer, connects the ESD circuit to a second terminal of the driver, receiver, or I/O circuit. The fourth interconnect provides a path for dissipating static electricity, protecting the sensitive circuits.
7. The chip of claim 1 further comprising a polymer layer over said passivation layer, wherein said polymer layer comprises a portion over said clock bus.
The chip described previously (with clock bus over a passivation layer) has a polymer layer over the passivation layer. This polymer layer covers at least a portion of the clock bus. The polymer layer acts as a protective layer or an additional dielectric layer.
8. The chip of claim 7 , wherein said polymer layer has a thickness greater than 2 micrometers.
The chip described previously (with a polymer layer over the passivation layer and clock bus) specifies that the polymer layer is thicker than 2 micrometers. The increased thickness can improve its protective qualities.
9. The chip of claim 1 , wherein said clock bus has a thickness greater than 1 micrometer.
The chip described previously (with a clock bus over a passivation layer) has a clock bus that is thicker than 1 micrometer. A thicker clock bus reduces resistance and improves signal integrity.
10. A chip comprising: a silicon substrate; a first internal circuit in or on said silicon substrate; a second internal circuit in or on said silicon substrate; a dielectric system over said silicon substrate; a first interconnecting structure over said silicon substrate and in said dielectric system, wherein said first interconnecting structure is connected to said first internal circuit; a second interconnecting structure over said silicon substrate and in said dielectric system, wherein said second interconnecting structure is connected to said second internal circuit; multiple metal layers in said dielectric system, wherein said dielectric system comprises multiple dielectric layers between said multiple metal layers; a passivation layer over said dielectric system and over said multiple metal layers, wherein said passivation layer comprises a nitride; a first via in said passivation layer, wherein said first via is connected to said first interconnecting structure; a second via in said passivation layer, wherein said second via is connected to said second interconnecting structure; and a clock bus over said passivation layer, wherein said clock bus has a thickness greater than 1 micrometer, wherein said clock bus is connected to said first and second vias, wherein said first internal circuit is connected to said second internal circuit through, in sequence, said first interconnecting structure, said first via, said clock bus, said second via and said second interconnecting structure.
A chip contains a silicon substrate with first and second internal circuits. A dielectric system covers the substrate, containing multiple dielectric layers and metal layers. First and second interconnect structures reside in this dielectric system, connecting to the respective internal circuits. A passivation layer (made of nitride) sits above the dielectric system and metal layers. First and second vias fill openings in the passivation layer, linking to the interconnect structures. A clock bus (thicker than 1 micrometer) lies above the passivation layer, connecting to both vias. This allows the first and second internal circuits to communicate: first interconnect -> first via -> clock bus -> second via -> second interconnect.
11. The chip of claim 10 further comprising a third internal circuit in or on said silicon substrate, wherein said first interconnecting structure is connected to said third internal circuit, wherein said first internal circuit is connected to said third internal circuit through said first interconnecting structure, wherein said third internal circuit is connected to said second internal circuit through, in sequence, said first interconnecting structure, said first via, said clock bus, said second via and said second interconnecting structure.
The chip described previously (a silicon substrate with first and second internal circuits connected by interconnects, vias, and a clock bus over a passivation layer) also includes a third internal circuit on the silicon substrate. The first interconnect structure connects to the third internal circuit. The first and third circuits communicate via the first interconnect. The third circuit communicates with the second circuit through the same path: first interconnect -> first via -> clock bus -> second via -> second interconnect.
12. The chip of claim 11 further comprising a fourth internal circuit in or on said silicon substrate, wherein said second interconnecting structure is connected to said fourth internal circuit, wherein said second internal circuit is connected to said fourth internal circuit through said second interconnecting structure, wherein said first internal circuit is connected to said fourth internal circuit through, in sequence, said first interconnecting structure, said first via, said clock bus, said second via and said second interconnecting structure, and wherein said third internal circuit is connected to said fourth internal circuit through, in sequence, said first interconnecting structure, said first via, said clock bus, said second via and said second interconnecting structure.
The chip described previously (a silicon substrate with first, second, and third internal circuits connected by interconnects, vias, and a clock bus over a passivation layer) also includes a fourth internal circuit on the silicon substrate. The second interconnect connects to this fourth circuit. The second and fourth circuits communicate via the second interconnect. Now, the first and fourth circuits communicate in sequence via the path: first interconnect -> first via -> clock bus -> second via -> second interconnect. Also, the third and fourth circuits communicate via the same path: first interconnect -> first via -> clock bus -> second via -> second interconnect.
13. The chip of claim 11 further comprising a fourth internal circuit in or on said silicon substrate, wherein said first interconnecting structure is connected to said fourth internal circuit, wherein said first internal circuit is connected to said fourth internal circuit through said first interconnecting structure, wherein said third internal circuit is connected to said fourth internal circuit through said first interconnecting structure, wherein said fourth internal circuit is connected to said second internal circuit through, in sequence, said first interconnecting structure, said first via, said clock bus, said second via and said second interconnecting structure.
The chip described previously (a silicon substrate with first, second, and third internal circuits connected by interconnects, vias, and a clock bus over a passivation layer) further includes a fourth internal circuit on the silicon substrate. The first interconnect connects to the fourth circuit. The first and fourth circuits communicate via the first interconnect. The third and fourth circuits communicate through the first interconnect as well. Finally, the fourth circuit connects to the second circuit in the path: first interconnect -> first via -> clock bus -> second via -> second interconnect.
14. The chip of claim 10 further comprising a driver, receiver or I/O circuit in or on said silicon substrate, a third interconnecting structure over said silicon substrate and in said dielectric system, wherein said third interconnecting structure is connected to a first terminal of said driver, receiver or I/O circuit, and a third via in said passivation layer, wherein said third via is connected to said third interconnecting structure and to said clock bus, wherein said first terminal is connected to said first internal circuit through, in sequence, said third interconnecting structure, said third via, said clock bus, said first via and said first interconnecting structure, and wherein said first terminal is connected to said second internal circuit through, in sequence, said third interconnecting structure, said third via, said clock bus, said second via and said second interconnecting structure.
The chip described previously (a silicon substrate with first and second internal circuits connected by interconnects, vias, and a clock bus over a passivation layer) also includes a driver, receiver, or I/O circuit on the silicon substrate. A third interconnect resides in the dielectric system, connected to a first terminal of this driver/receiver/I/O circuit. A third via exists in the passivation layer connecting the third interconnect to the clock bus. The first terminal connects to the first internal circuit through the following path: third interconnect -> third via -> clock bus -> first via -> first interconnect. It also connects to the second internal circuit via the path: third interconnect -> third via -> clock bus -> second via -> second interconnect.
15. The chip of claim 14 further comprising an ESD circuit in or on said silicon substrate, and a fourth interconnecting structure over said silicon substrate and in said dielectric system, wherein said ESD circuit is connected to a second terminal of said driver, receiver or I/O circuit through said fourth interconnecting structure.
The chip described previously (including driver/receiver/I/O and interconnects, vias, clock bus) also includes an ESD (electrostatic discharge) circuit located on the silicon substrate. A fourth interconnect, also located in the dielectric system, connects the ESD circuit to a second terminal of the driver, receiver, or I/O circuit. The fourth interconnect provides a path for dissipating static electricity, protecting the sensitive circuits.
16. The chip of claim 10 further comprising a polymer layer over said passivation layer, wherein said polymer layer comprises a portion over said clock bus.
The chip described previously (with clock bus over a passivation layer) has a polymer layer over the passivation layer. This polymer layer covers at least a portion of the clock bus. The polymer layer acts as a protective layer or an additional dielectric layer.
17. The chip of claim 16 , wherein said polymer layer has a thickness greater than 2 micrometers.
The chip described previously (with a polymer layer over the passivation layer and clock bus) specifies that the polymer layer is thicker than 2 micrometers. The increased thickness can improve its protective qualities.
18. A chip comprising: a silicon substrate; a metallization structure over said silicon substrate, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, wherein said metallization structure comprises an electroplated damascene metal; a dielectric layer between said first and second metal layers; a passivation layer over said metallization structure and said dielectric layer, wherein said passivation layer comprises a nitride layer, wherein a first opening in said passivation layer is over a first contact point of said metallization structure, and said first contact point is at a bottom of said first opening, wherein said first opening has a width between 0.5 and 30 micrometers; and a metal interconnect connected to said first contact point through said first opening, wherein said metal interconnect comprises electroplated copper.
A chip consists of a silicon substrate and a metallization structure on top. This metallization structure includes a first metal layer and a second metal layer over it, formed using electroplated damascene metal. A dielectric layer separates the two metal layers. A passivation layer (nitride) covers the metallization structure and dielectric layer. An opening (0.5-30 micrometers wide) in the passivation layer is positioned over a contact point on the metallization structure. A metal interconnect (electroplated copper) connects to this contact point through the opening.
19. The chip of claim 18 , wherein said metal interconnect comprises a ground interconnect.
The chip described previously (substrate, metallization, passivation, interconnect through an opening) specifies that the metal interconnect is a ground interconnect, providing a low-resistance path to ground.
20. The chip of claim 18 , wherein said metal interconnect comprises a signal interconnect.
The chip described previously (substrate, metallization, passivation, interconnect through an opening) specifies that the metal interconnect is a signal interconnect, carrying electrical signals between different parts of the circuit.
21. The chip of claim 18 further comprising a polymer layer over said passivation layer.
The chip described previously (substrate, metallization, passivation, interconnect through an opening) also includes a polymer layer over the passivation layer. The polymer layer can serve as a protective coating or an additional dielectric.
22. The chip of claim 18 further comprising a driver, receiver or I/O circuit in and on said silicon substrate.
The chip described previously (substrate, metallization, passivation, interconnect through an opening) also includes a driver, receiver, or I/O circuit formed on the silicon substrate.
23. The chip of claim 18 , wherein a second opening in said passivation layer is over a second contact point of said metallization structure, and said second contact point is at a bottom of said second opening, wherein said metal interconnect is connected to said second contact point through said second opening, wherein said first contact point is connected to said second contact point through said metal interconnect.
The chip described previously (substrate, metallization, passivation, interconnect through an opening) includes a second opening in the passivation layer over a second contact point on the metallization structure. The metal interconnect connects to this second contact point through the second opening. This allows the metal interconnect to electrically connect the first contact point to the second contact point, creating a path for current flow.
24. The chip of claim 23 , wherein a top surface of said metal interconnect has no access for external connection.
The chip described previously (metallization structure with two contact points connected via interconnect through openings in passivation) is designed such that the top surface of the metal interconnect is not accessible for external connections. The interconnect is fully buried beneath other layers of the chip.
25. The chip of claim 21 , wherein said polymer layer comprises a portion under said metal interconnect.
The chip described previously (passivation layer with polymer layer on top) specifies that the polymer layer extends under the metal interconnect, filling the space between the passivation layer and the metal interconnect.
26. The chip of claim 21 , wherein said polymer layer has a thickness greater than 2 micrometers.
The chip described previously (passivation layer with polymer layer on top) specifies the polymer layer is thicker than 2 micrometers. The greater thickness offers better insulation and protection.
27. The chip of claim 21 , wherein said polymer layer comprises a portion over said metal interconnect.
The chip described previously (passivation layer with polymer layer on top) specifies the polymer layer also extends over the metal interconnect, encapsulating it. This provides additional protection for the interconnect.
28. The chip of claim 18 , wherein said passivation layer further comprises an oxide layer.
The chip described previously (with a nitride passivation layer) also includes an oxide layer within the passivation layer. The passivation layer is therefore composed of both nitride and oxide.
29. The chip of claim 28 , wherein said nitride layer has a thickness greater than that of said oxide layer.
In the chip described previously (with both nitride and oxide layers in the passivation), the nitride layer is thicker than the oxide layer. This indicates that the nitride layer plays a more prominent role in the passivation.
30. The chip of claim 18 , wherein said metal interconnect has a thickness greater than 1 micrometer.
The chip described previously (with a metal interconnect through a passivation opening) has a metal interconnect with a thickness greater than 1 micrometer. A thicker interconnect offers lower resistance.
31. A chip comprising: a silicon substrate; a first metallization structure over said silicon substrate, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, wherein said first metallization structure comprises an electroplated damascene metal; a dielectric layer between said first and second metal layers; a passivation layer over said first metallization structure and said dielectric layer, wherein said passivation layer comprises a nitride layer, wherein a first opening in said passivation layer is over a first contact point of said first metallization structure, and said first contact point is at a bottom of said first opening, wherein said first opening has a width between 0.5 and 30 micrometers; and a second metallization structure on said first contact point and over said passivation layer, wherein said second metallization structure is connected to said first contact point through said first opening, wherein said second metallization structure comprises electroplated copper.
A chip contains a silicon substrate and a first metallization structure on top. This metallization structure includes a first metal layer and a second metal layer over it, formed using electroplated damascene metal. A dielectric layer separates the two metal layers. A passivation layer (nitride) covers the first metallization structure and dielectric layer. An opening (0.5-30 micrometers wide) in the passivation layer is positioned over a contact point on the metallization structure. A second metallization structure (electroplated copper) connects to this contact point through the opening, extending above the passivation layer.
32. The chip of claim 31 , wherein a second opening in said passivation layer is over a second contact point of said first metallization structure, and said second contact point is at a bottom of said second opening, wherein said second metallization structure is connected to said second contact point through said second opening, wherein said first contact point is connected to said second contact point through said second metallization structure.
The chip described previously (silicon substrate with a first and second metallization structure) has a second opening in said passivation layer is over a second contact point of said first metallization structure, and said second contact point is at a bottom of said second opening, wherein said second metallization structure is connected to said second contact point through said second opening, wherein said first contact point is connected to said second contact point through said second metallization structure
33. The chip of claim 31 , wherein said passivation layer further comprises an oxide layer.
The chip described previously (with a nitride passivation layer) also includes an oxide layer within the passivation layer. The passivation layer is therefore composed of both nitride and oxide.
34. The chip of claim 33 , wherein said nitride layer has a thickness greater than that of said oxide layer.
In the chip described previously (with both nitride and oxide layers in the passivation), the nitride layer is thicker than the oxide layer. This indicates that the nitride layer plays a more prominent role in the passivation.
35. The chip of claim 31 further comprising a polymer layer on said passivation layer, wherein said second metallization structure is further on a top surface of said polymer layer.
The chip previously described has a polymer layer on the passivation layer. The second metallization structure (which connects to the first metallization structure through an opening in the passivation layer) also extends onto the top surface of the polymer layer, indicating the second metallization structure is formed after the polymer layer deposition.
36. The chip of claim 35 , wherein said polymer layer has a thickness between 2 and 150 micrometers.
The chip described previously (with a polymer layer on the passivation layer) has a polymer layer with a thickness between 2 and 150 micrometers. This thickness range offers flexibility in design and application, allowing for tuning of dielectric and planarization properties.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
September 17, 2007
July 9, 2013
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