In one embodiment, the present invention includes a processor having at least one core and uncore logic. The uncore logic can include a home agent to act as a guard to control access to a memory region. Either in the home agent or another portion of the uncore logic, a directory cache may be provided to store ownership information for a portion of the memory region owned by an agent coupled to the processor. In this way, when an access request for the memory region misses in the directory cache, a memory transaction can be avoided. Other embodiments are described and claimed.
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1. An apparatus comprising: a processor having at least one core and uncore logic, the uncore logic having a home agent to control access to a memory region, the home agent including a directory cache to store only ownership information for a portion of the memory region owned by a peripheral agent coupled to the processor via an input/output hub.
The system includes a processor with one or more cores and supporting "uncore" logic. Within this uncore logic, a "home agent" controls access to a specific memory region. The home agent contains a "directory cache". This cache stores ownership information *only* for portions of that memory region that are currently owned by a peripheral device (like a GPU or network card). The peripheral connects to the processor via an input/output hub. The directory cache helps manage memory access from peripherals.
2. The apparatus of claim 1 , wherein the memory region includes a directory to indicate ownership of lines within the memory region.
The apparatus described previously (a processor with a home agent and directory cache managing peripheral access to memory) involves a memory region that contains a "directory". This directory indicates which lines or blocks of data *within* that memory region are owned by different agents (e.g., the processor cores or the peripheral device). It is an extra level of ownership granularity.
3. The apparatus of claim 2 , wherein the home agent is to not send a request to the memory region to read the directory responsive to an access request from the at least one core if an address of the access request misses in the directory cache, and the home agent is to send a grant message to the at least one core responsive to the miss.
In the apparatus described previously (a processor with a home agent and directory cache managing peripheral access to memory, where the memory region contains a directory), if a core makes an access request to memory and the address for that request *isn't* found in the directory cache (a "miss"), the home agent avoids sending a request to the main memory to consult its directory. Instead, the home agent immediately sends a "grant" message back to the requesting core, giving the core access. The directory cache accelerates memory access by the cores.
4. The apparatus of claim 3 , wherein the home agent is to send the request to the memory region to read the directory responsive to the access request if the address of the access request hits in the directory cache.
Building on the previous apparatus (a processor with a home agent and directory cache managing peripheral access to memory), if a core makes an access request to memory and the address for that request *is* found in the directory cache (a "hit"), the home agent *does* send a request to the main memory to read the directory stored there. The directory cache forwards to the main memory.
5. The apparatus of claim 2 , wherein the home agent is to insert an entry into the directory cache for a memory region portion responsive to a request for ownership of the memory region portion by the peripheral agent, and to forward the request to the memory region.
Using the previously described apparatus (a processor with a home agent and directory cache managing peripheral access to memory, where the memory region contains a directory), when a peripheral device requests ownership of a portion of the memory region, the home agent inserts an entry into its directory cache indicating this request. Simultaneously, the home agent forwards the ownership request to the actual memory itself to handle. The directory cache helps track ownership changes from peripherals.
6. The apparatus of claim 5 , wherein the memory region is to update the directory to indicate ownership of the memory region portion by the peripheral agent.
Continuing from the previous apparatus (a processor with a home agent and directory cache managing peripheral access to memory where the directory cache inserts an entry for a peripheral device's ownership request), after the home agent forwards the peripheral's request, the memory *updates* its own directory to reflect that the peripheral device now owns the specified portion of the memory region. This keeps the memory system consistent.
7. The apparatus of claim 1 , wherein the directory cache includes a plurality of entries each corresponding to an available memory transaction from the peripheral agent.
In the apparatus (a processor with a home agent and directory cache managing peripheral access to memory), the directory cache has multiple entries, and each entry corresponds to a single available memory transaction that can be initiated by the peripheral agent coupled via the I/O hub. This limits how many memory requests the IO device can own.
8. The apparatus of claim 7 , wherein the directory cache is only to store ownership information for data owned by the input/output hub.
In the apparatus (a processor with a home agent and directory cache managing peripheral access to memory, where the directory cache includes a plurality of entries corresponding to available memory transactions from the peripheral agent), the directory cache *only* stores ownership information for data that is owned by the input/output hub. It doesn't track ownership of data owned by other agents (like the processor cores themselves).
9. A method comprising: receiving a request for ownership of data associated with an address of a memory coupled to a processor in a home agent of the processor from a peripheral device coupled to the processor; updating a directory cache of the home agent to indicate the request for ownership, and forwarding a message regarding the request for ownership to the memory, the directory cache to store only ownership information for a portion of the memory owned by the peripheral device; and updating a directory in the memory to indicate ownership of the data associated with the address by the peripheral device, and forwarding a grant message from the directory cache to the peripheral device.
A method involves a home agent in a processor receiving a request from a peripheral device for ownership of data at a specific memory address. The home agent updates its directory cache to record this ownership request *and* forwards the request to the memory itself. The memory then updates *its* directory to indicate the peripheral device as the owner of the data. Finally, the directory cache sends a "grant" message to the peripheral device. The directory cache stores only the ownership for the peripheral.
10. The method of claim 9 , further comprising: receiving a second request for ownership in the home agent from a local core; and determining whether an address of the second request for ownership from the local core misses in the directory cache, and if so, granting exclusive access to data present at the address of the second request for ownership to the local core, without sending a transaction to the memory.
Building upon the previous method (home agent updates directory cache and forwards request to memory for peripheral device ownership), if the home agent receives a *second* request for ownership from a processor core and the address of *this* request is *not* found in the directory cache (a "miss"), the home agent grants exclusive access to the core *without* sending any transaction to the memory. This accelerates memory access from the cores.
11. The method of claim 9 , further comprising: receiving a second request for ownership in the home agent from a local core; and determining whether an address of the second request for ownership from the local core hits in the directory cache, and if so, forwarding a second message regarding the request to the memory.
Building upon the method where a peripheral requests ownership of data (home agent updates directory cache and forwards request to memory for peripheral device ownership), if the home agent receives a *second* request for ownership from a processor core and the address of *this* request *is* found in the directory cache (a "hit"), the home agent forwards *another* message regarding the core's request to the main memory. The directory cache enables forwarding.
12. The method of claim 11 , further comprising determining whether the address of the second request for ownership hits in a directory of the memory, and if so, handling the request according to a cache coherency protocol for a system including the processor.
Continuing from the previous method (home agent forwards a core's ownership request to memory if it hits in the directory cache), after the core's request is forwarded to memory, the method determines whether the address of that request is found in the memory's directory. If it *is* found, the request is handled according to the standard cache coherency protocol for the system. This makes sure memory is kept up to date.
13. The method of claim 11 , further comprising determining whether the address of the second request for ownership hits in a directory of the memory, and if not, sending a grant of exclusive ownership of data at the address of the second request to the local core.
Continuing from the method where the home agent forwards a core's ownership request to the memory if it hits in the directory cache, after the core's request is forwarded to the memory, the method determines whether the address of that request is found in the memory's directory. If it is *not* found, the system grants exclusive ownership of the data at that address to the processor core. This resolves ownership if there is a miss in the memory.
14. The method of claim 9 , further comprising providing a 1:1 correspondence between the directory cache and a number of available transactions from an input/output (I/O) hub coupled to the processor, and only storing information regarding transactions from the I/O hub in the directory cache.
Building on the initial method (home agent updates directory cache and forwards request to memory for peripheral device ownership), there's a direct, one-to-one correspondence between the entries in the directory cache and the number of available transactions from the input/output hub. The directory cache only holds information about transactions originating from the I/O hub. This limits the I/O device requests to the number of entries.
15. A system comprising: a processor having at least one core and a directory cache, wherein the directory cache is to prevent a memory read to a directory present in a system memory coupled to the processor when an address of the memory access request does not hit in the directory cache, the directory cache to store entries only for ownership of addresses within the system memory by an input/output (IO) device coupled to the processor; and the system memory coupled to the processor, wherein the system memory comprises a dynamic random access memory (DRAM).
A system includes a processor with at least one core and a directory cache. This cache prevents a read to a directory in the system memory (which is DRAM) when a memory access request's address isn't in the directory cache. The cache stores entries *only* for addresses in system memory owned by an I/O device. The system memory (DRAM) is connected to the processor. The directory cache accelerates memory access.
16. The system of claim 15 , wherein the processor is to forward the memory read to the directory when the memory access request address hits in the directory cache.
In the system (processor with directory cache preventing memory reads, with DRAM memory), the processor *does* forward a memory read request to the memory's directory when the memory access request's address *is* found (hits) in the directory cache.
17. The system of claim 15 , wherein the memory access request is from a core of the processor.
The system (processor with directory cache preventing memory reads, with DRAM memory) uses a memory access request coming *from a core* within the processor. This describes where the memory request originates.
18. The system of claim 15 , wherein when the address of the memory access request does not hit in the directory cache, the processor is to send a grant message to the at least one core responsive to the miss.
In the system (processor with directory cache preventing memory reads, with DRAM memory), when a memory access request's address is *not* found (misses) in the directory cache, the processor sends a "grant" message back to the core that made the request. This provides fast access when the directory cache has no entry.
19. The system of claim 15 , wherein the processor includes an uncore logic, the uncore logic having a home agent, and wherein the directory cache is associated with the home agent.
In the system (processor with directory cache preventing memory reads, with DRAM memory), the processor includes "uncore logic," containing a "home agent." The directory cache is associated with this home agent. This defines where the directory cache is located in the processor's structure.
20. The system of claim 15 , wherein the directory cache has a 1:1 mapping between a number of entries in the directory cache and a number of lines that the IO device can own in the DRAM.
In the system (processor with directory cache preventing memory reads, with DRAM memory), there's a one-to-one mapping between the number of entries in the directory cache and the number of memory lines (or blocks) that the I/O device can own in the DRAM memory. The number of IO device lines equals the directory cache entry count.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
November 23, 2010
July 16, 2013
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