Memories, clock generators and methods for providing an output clock signal are disclosed. One such method includes delaying a buffered clock signal by a adjustable delay to provide an output clock signal, providing a feedback clock signal from the output clock signal, and adjusting a duty cycle of the buffered clock signal based at least in part on the feedback clock signal. An example clock generator includes a forward clock path configured to provide a delayed output clock signal from a clock driver circuit, and further includes a feedback clock path configured to provide a feedback clock signal based at least in part on the delayed output clock signal, for example, frequency dividing the delayed output clock signal. The feedback clock path further configured to control adjustment a duty cycle of the buffered input clock signal based at least in part on the feedback clock signal.
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1. A clock divider circuit, comprising: an output stage configured to provide a divided clock signal responsive first and second input signals and a clock signal to be divided; and a plurality of clock divider stages coupled to provide the first and second input signals to the output stage in response to the clock signal to be divided, the clock divider stages configured to divide the clock signal to be divided by N, wherein N is a value that is selected from a set of values that includes both even and odd values.
A clock divider circuit reduces the frequency of a clock signal by a factor of N, where N can be either an even or odd number. The circuit contains an output stage that generates the divided clock signal based on first and second input signals, along with the original clock signal. A series of clock divider stages provide these first and second input signals to the output stage, effectively dividing the input clock signal by the desired N value.
2. The clock divider circuit of claim 1 wherein the plurality of clock divider stages comprises: a first clock divider stage coupled to the output stage and configured to provide the first and second input signals responsive to the clock signal to be divided, the first input signal based at least in part on the second input signal when the first clock divider stage is enabled and based at least in part on a stage output signal when the first clock divider stage is disabled; and at least one of a second clock divider stage coupled to the first clock divider stage to receive the first input signal, the at least one of the second clock divider stage configured to provide the first input signal responsive to the clock signal to be divided to a stage output when enabled.
The clock divider circuit has a cascade of clock divider stages. A first stage, connected to the output stage, generates the first and second input signals for the output. When this first stage is enabled, the first input signal is derived from the second input signal. However, when the first stage is disabled, the first input signal is instead derived from a "stage output signal" of the first stage. At least one additional clock divider stage receives the first input signal and produces the "stage output signal" when enabled.
3. The clock divider circuit of claim 2 wherein the first clock divider stage comprises a multiplexer configured to receive the first input signal and the stage output signal and provide one or the other based on the enablement of the first clock divider stage; a first latch circuit having an input coupled to the multiplexer and clocked by the clock signal to be divided to provide the second input signal based on the signal from the multiplexer; logic circuitry coupled to an output of the first latch circuit and configured to provide an output signal based at least in part on the second input signal and whether the clock signal to be divided is an even or odd value; and a second latch circuit having an input coupled to the logic circuitry and clocked by the clock signal to be divided to provide the first input signal based at least in part on the output signal from the logic circuitry.
Within the first clock divider stage of the clock divider circuit, a multiplexer selects between the first input signal and a stage output signal based on whether the first clock divider stage is enabled. A first latch captures the multiplexer output, triggered by the clock signal to be divided, producing the second input signal. Logic circuitry analyzes the second input signal and whether N is even or odd to generate an output signal. A second latch then captures this output signal, again triggered by the clock signal to be divided, generating the first input signal to the multiplexer.
4. The clock divider circuit of claim 1 wherein the plurality of clock divider stages comprises: N clock divider stages coupled to the output stage and through which the divided clock signal is propagated responsive to the clock signal to be divided to provide the first and second input signals, the N clock divider stages configured to provide a divided clock signal having a frequency 1/N of the clock signal to be divided, where N is an even or odd value.
The clock divider circuit uses N clock divider stages chained together. The divided clock signal is propagated through these N stages in response to the input clock signal to create the first and second input signals for the output stage. These stages work together to produce a divided clock signal with a frequency that is 1/N of the original clock signal, where N can be either an even or an odd number.
5. The clock divider circuit of claim 4 wherein each of the N clock divider stages comprises first and second latch circuits clocked by the clock signal to be divided, each of the latch circuits latching in response to a different phase of the clock signal to be divided.
Each of the N clock divider stages in the clock divider circuit includes two latch circuits. Both latch circuits are clocked by the clock signal to be divided. Crucially, the two latch circuits are triggered by opposite phases of the clock signal.
6. A method for dividing a clock signal, comprising: providing the clock signal and a first and second input signal; latching one of the first and second input signals with respect to the clock signal wherein the latching divides the clock signal by an even or odd value resulting in a divided clock signal; and activating first and second clocked inverters for a different phase of the clock signal to output the divided clock signal responsive to the clock signal and the first and second input signal.
A method for dividing a clock signal involves supplying the clock signal along with first and second input signals. One of these input signals is latched relative to the clock signal. This latching process divides the clock signal by either an even or odd number, resulting in a divided clock signal. First and second clocked inverters are then activated during different phases of the clock signal to output the divided clock signal. These inverters respond to both the clock signal and the first/second input signals.
7. The method of claim 6 , wherein outputting the divided clock signal comprises inverting a result of the latching responsive to the clock signal.
When outputting the divided clock signal (obtained from latching one of the first and second input signals with respect to the clock signal wherein the latching divides the clock signal by an even or odd value resulting in a divided clock signal; and activating first and second clocked inverters for a different phase of the clock signal to output the divided clock signal responsive to the clock signal and the first and second input signal), the output is created by inverting the result of the latching operation, where the inverting is responsive to the clock signal.
8. The method of claim 7 , wherein the inverting corresponds to different phases of the clock signal.
The inverting process to output the divided clock signal (obtained from latching one of the first and second input signals with respect to the clock signal wherein the latching divides the clock signal by an even or odd value resulting in a divided clock signal; and activating first and second clocked inverters for a different phase of the clock signal to output the divided clock signal responsive to the clock signal and the first and second input signal) corresponds to different phases of the clock signal.
9. The method of claim 6 , wherein the latching comprises latching one of the first and second signals multiple times.
In the clock division method (providing the clock signal and a first and second input signal; latching one of the first and second input signals with respect to the clock signal wherein the latching divides the clock signal by an even or odd value resulting in a divided clock signal; and activating first and second clocked inverters for a different phase of the clock signal to output the divided clock signal responsive to the clock signal and the first and second input signal), the latching one of the first and second signals happens multiple times.
10. The method of claim 9 , wherein, the latching further comprises multiplexing one of the first and second signals between multiple latchings.
The clock division method (providing the clock signal and a first and second input signal; latching one of the first and second input signals with respect to the clock signal wherein the latching divides the clock signal by an even or odd value resulting in a divided clock signal; and activating first and second clocked inverters for a different phase of the clock signal to output the divided clock signal responsive to the clock signal and the first and second input signal) includes latching one of the first and second signals multiple times and incorporates a multiplexing step, where one of the first or second signals is switched between multiple latching operations.
11. The method of claim 10 , wherein the multiplexing is responsive to a control signal.
The clock division method (providing the clock signal and a first and second input signal; latching one of the first and second input signals with respect to the clock signal wherein the latching divides the clock signal by an even or odd value resulting in a divided clock signal; and activating first and second clocked inverters for a different phase of the clock signal to output the divided clock signal responsive to the clock signal and the first and second input signal) includes latching one of the first and second signals multiple times, multiplexing one of the first and second signals between multiple latchings, where the multiplexing action is controlled by a separate control signal.
12. The method of claim 11 , wherein the multiplexing determines whether the clock signal is divided by an even or odd value.
The clock division method (providing the clock signal and a first and second input signal; latching one of the first and second input signals with respect to the clock signal wherein the latching divides the clock signal by an even or odd value resulting in a divided clock signal; and activating first and second clocked inverters for a different phase of the clock signal to output the divided clock signal responsive to the clock signal and the first and second input signal) includes latching one of the first and second signals multiple times, multiplexing one of the first and second signals between multiple latchings, where the multiplexing action determines whether the clock signal is divided by an even or an odd value.
13. A clock divider circuit, comprising: a plurality of clock divider stages and an output stage configured to be selectively coupled to each other to provide an output clock signal having a frequency that is either an even or odd division of a clock signal to be divided, wherein the output stage includes first and second clocked inverters, wherein the first and second clocked inverters are configured to be active for a different phase of the clock signal to be divided to provide the output clock signal.
A clock divider circuit consists of multiple clock divider stages and an output stage. These stages can be selectively interconnected to produce an output clock signal whose frequency is either an even or an odd division of the original clock signal. The output stage uses two clocked inverters. These inverters are active during different phases of the input clock signal, contributing to the generation of the output clock signal.
14. The clock divider circuit of claim 13 , wherein each of the plurality of clock divider stages comprises a multiplexer configured to receive control signals, wherein the control signals enable the selective coupling between clock divider stages.
Each clock divider stage in the clock divider circuit (a plurality of clock divider stages and an output stage configured to be selectively coupled to each other to provide an output clock signal having a frequency that is either an even or odd division of a clock signal to be divided, wherein the output stage includes first and second clocked inverters, wherein the first and second clocked inverters are configured to be active for a different phase of the clock signal to be divided to provide the output clock signal) contains a multiplexer. This multiplexer receives control signals that enable the selective connections between different clock divider stages.
15. The clock divider circuit of claim 13 , wherein the output stage comprises: logic circuitry configured to provide an output signal based at least in part on whether the clock signal to be divided is an even or odd value.
The output stage of the clock divider circuit (a plurality of clock divider stages and an output stage configured to be selectively coupled to each other to provide an output clock signal having a frequency that is either an even or odd division of a clock signal to be divided, wherein the output stage includes first and second clocked inverters, wherein the first and second clocked inverters are configured to be active for a different phase of the clock signal to be divided to provide the output clock signal) includes logic circuitry that determines whether the clock signal is being divided by an even or odd value, and uses that information to generate an appropriate output signal.
16. A clock divider circuit, comprising: N clock divider stages coupled to each other through which a divided clock signal is propagated responsive to a clock signal to be divided, the N clock divider stages configured to provide a divided clock signal having a frequency of 1/N of the clock signal to be divided, where N is an even or odd value; and first and second clocked inverters, wherein the first and second clocked inverters each configured to be active for a different phase of the clock signal to be divided to provide the divided clock signal.
A clock divider circuit uses N clock divider stages connected in a chain. A divided clock signal propagates through these stages, responding to the input clock signal. The N stages are designed to generate an output signal with a frequency of 1/N of the input clock, where N can be either even or odd. The circuit also includes two clocked inverters. Each inverter is activated during a different phase of the input clock signal, to generate the final divided clock signal.
17. The clock divider circuit of claim 16 , wherein each of the N clock divider stages comprises first and second latch circuits clocked by the clock signal to be divided, each of the latch circuits latching in response to a different phase of the clock signal to be divided.
In the clock divider circuit (N clock divider stages coupled to each other through which a divided clock signal is propagated responsive to a clock signal to be divided, the N clock divider stages configured to provide a divided clock signal having a frequency of 1/N of the clock signal to be divided, where N is an even or odd value; and first and second clocked inverters, wherein the first and second clocked inverters each configured to be active for a different phase of the clock signal to be divided to provide the divided clock signal), each of the N divider stages contains two latch circuits. These latch circuits are both clocked by the input clock signal, but they latch on different phases of the clock.
18. The clock divider circuit of claim 17 , wherein the first and second latch circuits are coupled in series.
In the clock divider circuit (N clock divider stages coupled to each other through which a divided clock signal is propagated responsive to a clock signal to be divided, the N clock divider stages configured to provide a divided clock signal having a frequency of 1/N of the clock signal to be divided, where N is an even or odd value; and first and second clocked inverters, wherein the first and second clocked inverters each configured to be active for a different phase of the clock signal to be divided to provide the divided clock signal; wherein each of the N clock divider stages comprises first and second latch circuits clocked by the clock signal to be divided, each of the latch circuits latching in response to a different phase of the clock signal to be divided), the first and second latch circuits within each stage are connected in series.
19. The clock divider circuit of claim 17 , wherein the first and second latch circuits are coupled in parallel.
In the clock divider circuit (N clock divider stages coupled to each other through which a divided clock signal is propagated responsive to a clock signal to be divided, the N clock divider stages configured to provide a divided clock signal having a frequency of 1/N of the clock signal to be divided, where N is an even or odd value; and first and second clocked inverters, wherein the first and second clocked inverters each configured to be active for a different phase of the clock signal to be divided to provide the divided clock signal; wherein each of the N clock divider stages comprises first and second latch circuits clocked by the clock signal to be divided, each of the latch circuits latching in response to a different phase of the clock signal to be divided), the first and second latch circuits within each stage are connected in parallel.
20. The clock divider circuit of claim 16 , wherein for odd values of N, the duty cycle error of the divided clock signal is 1/N of the clock signal to be divided.
When the clock divider circuit (N clock divider stages coupled to each other through which a divided clock signal is propagated responsive to a clock signal to be divided, the N clock divider stages configured to provide a divided clock signal having a frequency of 1/N of the clock signal to be divided, where N is an even or odd value; and first and second clocked inverters, wherein the first and second clocked inverters each configured to be active for a different phase of the clock signal to be divided to provide the divided clock signal) is used to divide by an odd number N, the duty cycle error of the divided clock signal is 1/N of the original clock signal's period.
21. The clock divider circuit of claim 16 , wherein an input of either the first or second clocked inverter is driven to be outputted as the divided clock signal.
In the clock divider circuit (N clock divider stages coupled to each other through which a divided clock signal is propagated responsive to a clock signal to be divided, the N clock divider stages configured to provide a divided clock signal having a frequency of 1/N of the clock signal to be divided, where N is an even or odd value; and first and second clocked inverters, wherein the first and second clocked inverters each configured to be active for a different phase of the clock signal to be divided to provide the divided clock signal), the final divided clock signal is generated by directly driving the output using either the input of the first clocked inverter or the input of the second clocked inverter.
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July 3, 2012
July 23, 2013
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