A computer system includes a processor, a submodule connected to the processor, an external access monitor configured to monitor a data transfer between the processor and the submodule, and a synchronization/desynchronization controller configured to synchronize or desynchronize the clock of the processor with respect to the clock of the submodule, depending on the result of the monitoring. Specifically, the processor clock is synchronized to the submodule clock when the frequency of access to the submodule by the processor is high, and the processor clock is desynchronized with respect to the submodule clock when the access frequency is low.
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1. A computer system comprising: a processor; a submodule connected to the processor; an external access monitor configured to monitor a data transfer between the processor and the submodule; and a synchronization/desynchronization controller configured to synchronize or desynchronize a clock of the processor with respect to a clock of the submodule, depending on a result of the monitoring by the external access monitor, wherein the external access monitor includes an access measurer configured to measure the number of accesses per predetermined period between the processor and the submodule, and a comparator configured to compare a result of the measurement by the access measurer with a predetermined count value, and the synchronization/desynchronization controller, when a result of the comparison with the predetermined count value by the comparator indicates that the number of accesses per predetermined period is the predetermined count value or more, synchronizes the clock of the processor to the clock of the submodule, and when the result of the comparison with the predetermined count value by the comparator indicates that the number of accesses per predetermined period is less than the predetermined count value, desynchronizes the clock of the processor with respect to the clock of the submodule.
A computer system manages processor/submodule clock synchronization. It has a processor, a connected submodule, an external access monitor tracking data transfers between them, and a synchronization/desynchronization controller. The controller syncs or desyncs the processor clock to the submodule clock based on transfer activity. The access monitor counts accesses per period using an access measurer. A comparator compares this count against a threshold. If the access count meets or exceeds the threshold, the controller synchronizes the clocks. If the count is below the threshold, the controller desynchronizes them. This dynamic adjustment optimizes power consumption and performance.
2. The computer system of claim 1 , wherein the synchronization/desynchronization controller, when the clock of the processor is transitioned from the asynchronous mode to the synchronous mode with respect to the submodule, sets a frequency of the clock of the processor to a highest one of frequencies at which the clock of the processor is synchronous with the clock of the submodule.
Building upon the clock synchronization system: when transitioning from asynchronous to synchronous mode, the synchronization/desynchronization controller sets the processor clock frequency to the *highest* available frequency at which synchronous operation with the submodule clock is possible. This ensures maximal performance once synchronization is deemed necessary. This allows the processor to operate at its fastest supported clock speed that is still synchronized to the submodule.
3. The computer system of claim 1 , wherein the synchronization/desynchronization controller, when the clock of the processor is transitioned from the asynchronous mode to the synchronous mode with respect to the submodule, transitions the clock of the processor to one closest to a frequency obtained immediately prior to the transition to the synchronous mode of frequencies at which the clock of the processor is synchronous with the clock of the submodule.
Building upon the clock synchronization system: when transitioning from asynchronous to synchronous mode, the synchronization/desynchronization controller adjusts the processor clock to the synchronous frequency that is *closest* to the processor clock's frequency immediately *before* the transition. Instead of always picking the highest possible synchronized frequency, this attempts to provide a smoother, less jarring transition in clock speed, minimizing potential disruption and maximizing stability.
4. The computer system of claim 1 , wherein the synchronization/desynchronization controller, when the clock of the processor is transitioned from the synchronous mode to the asynchronous mode with respect to the submodule, sets a frequency of the clock of the processor to a highest one of frequencies at which the processor can operate.
Building upon the clock synchronization system: when transitioning from synchronous to asynchronous mode, the synchronization/desynchronization controller sets the processor clock to the *highest* frequency at which the processor can operate. This optimizes processor performance during periods of infrequent submodule access by allowing the processor to run at its full speed without needing to be synchronized to the potentially slower submodule.
5. The computer system of claim 1 , wherein the synchronization/desynchronization controller includes a frequency holder configured to store a frequency of the clock of the processor obtained after the transition of the clock of the processor between the synchronous and asynchronous modes, and transitions the clock of the processor to a frequency previously stored in the frequency holder.
Building upon the clock synchronization system: the synchronization/desynchronization controller includes a "frequency holder" that stores the processor clock frequency each time the system switches between synchronous and asynchronous modes. Upon a subsequent transition, the controller restores the processor clock to its *previously stored* frequency. This facilitates quicker and more predictable transitions, improving system stability and potentially optimizing performance by reverting to known-good clock settings.
6. The computer system of claim 1 , wherein the synchronization/desynchronization controller transitions the clock of the processor to a frequency arbitrarily set by the user.
Building upon the clock synchronization system: the synchronization/desynchronization controller allows the user to *arbitrarily set* the processor clock frequency. This provides user control over the trade-off between performance and power consumption, enabling customization based on specific workload or system requirements. The user can manually override the automatic synchronization/desynchronization behavior.
7. The computer system of claim 1 , further comprising: a section configured to enable or disable a control with respect to the clock of the processor performed by the synchronization/desynchronization controller.
Building upon the clock synchronization system: the system includes a section that enables or disables the synchronization/desynchronization controller's control over the processor clock. This provides a way to bypass the automatic clock management and potentially use a fixed clock speed, useful for debugging, testing, or scenarios where controlled performance is more important than dynamic adjustment. The user can switch clock control on and off.
8. The computer system of claim 1 , wherein a period of time during which the number of accesses is measured by the access measurer can be arbitrarily changed by the user.
Building upon the clock synchronization system: the period over which the access measurer counts accesses between the processor and submodule is *user-configurable*. This allows adjustment of the system's sensitivity to access patterns, enabling optimization for different workloads. A shorter period makes the system more responsive to changes, while a longer period provides a smoother response by averaging access counts over a larger time window.
9. The computer system of claim 1 , wherein the synchronization/desynchronization controller includes a transition address holder configured to store an execution address of the processor obtained after the transition of the clock of the processor between the synchronous and asynchronous modes, and previously synchronizes or desynchronizes the clock of the processor with respect to the clock of the submodule before the processor executes the execution address stored in the transition address holder.
Building upon the clock synchronization system: the synchronization/desynchronization controller has a "transition address holder" that stores the processor's *execution address* after each clock mode transition. Before the processor executes this address, the controller ensures the processor clock is synchronized or desynchronized with respect to the submodule clock. This prevents issues caused by code being executed with the wrong clock configuration, avoiding errors or unexpected behavior.
10. The computer system of claim 1 , wherein the synchronization/desynchronization controller includes a transition address holder configured to store an execution address of the processor obtained after the transition of the clock of the processor between the synchronous and asynchronous modes, an operation period measurer configured to measure a synchronous/asynchronous operation period of the clock of the processor, and a comparator configured to compare a result of the measurement by the operation period measurer with a predetermined period, and when a result of the comparison with the predetermined period by the comparator indicates that an interval between transitions of the clock of the processor is the predetermined period or more, an execution address of the processor is stored into the transition address holder, and when the result of the comparison with the predetermined period by the comparator indicates that the interval between transitions of the clock of the processor is less than the predetermined period, the execution address of the processor is not stored into the transition address holder, and the clock of the processor is previously synchronized or desynchronized with respect to the clock of the submodule before the execution address stored in the transition address is executed by the processor.
Building upon the clock synchronization system: the synchronization/desynchronization controller features a "transition address holder," an "operation period measurer," and a comparator. The operation period measurer tracks the time between clock mode transitions (sync/async). The comparator compares this interval to a preset period. If the interval exceeds the threshold, the processor's execution address is stored in the holder. If the interval is shorter, the address isn't stored. Before executing a stored address, the controller synchronizes/desynchronizes the clocks, preventing issues caused by quickly flip-flopping between sync/async and ensuring synchronization happens *before* critical code runs.
11. The computer system of claim 10 , wherein the predetermined period with which the result of the measurement by the operation period measurer is compared can be arbitrarily changed by the user.
Building upon the clock synchronization system with address-aware synchronization: the *predetermined period* used to evaluate clock transition frequency (described in the previous address-aware clock management description) is *user-configurable*. The user can adjust how frequently address storing takes place allowing the adjustment of sensitivity to access patterns, enabling optimization for different workloads.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
March 16, 2011
August 6, 2013
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