An access node of a communication system is configured to control crosstalk between channels of the system. Vectoring circuitry in the access node estimates crosstalk between channels of the system, generates a compressed representation of the crosstalk estimates, and generates compensated signals based on the compressed representation of the crosstalk estimates. The compressed representation comprises a value array and an index array, with the value array comprising selected values from each of a plurality of rows of a matrix representation of the crosstalk estimates, and the index array identifying locations of the selected values in the matrix representation of the crosstalk estimates. The compensated signals may be pre-compensated signals or post-compensated signals.
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1. A method of controlling crosstalk between channels of a communication system, comprising: estimating crosstalk between channels of the system; generating a compressed representation of the crosstalk estimates; and generating compensated signals based on the compressed representation of the crosstalk estimates; wherein the compressed representation comprises a value array and an index array, the value array comprising selected values from each of a plurality of rows of a matrix representation of the crosstalk estimates and the index array identifying locations of the selected values in the matrix representation of the crosstalk estimates.
A method for reducing crosstalk (signal interference) between communication channels. The method involves: 1) Measuring the crosstalk between each channel. 2) Creating a compressed representation of these crosstalk measurements. This compressed representation includes a "value array" (containing selected crosstalk values from rows in a crosstalk matrix) and an "index array" (indicating the original locations of those selected values within the matrix). 3) Generating compensated signals based on this compressed crosstalk information to counteract the interference.
2. The method of claim 1 wherein the step of generating compensated signals based on the compressed representation of the crosstalk estimates comprises generating pre-compensated signals.
This is the crosstalk reduction method described previously. The step of generating compensated signals specifically involves creating pre-compensated signals. These are signals adjusted *before* transmission to proactively cancel out the expected crosstalk.
3. The method of claim 2 further comprising the step of transmitting the pre-compensated signals from an access node of system to respective network terminals of the system over respective ones of the channels.
This expands on the pre-compensation method described earlier. After generating the pre-compensated signals, an access node (like a DSLAM) transmits these modified signals to individual network terminals (e.g., modems) over their respective communication channels. This pre-compensation aims to reduce crosstalk at the receiving end.
4. The method of claim 1 wherein the step of generating compensated signals based on the compressed representation of the crosstalk estimates comprises generating post-compensated signals.
This is the crosstalk reduction method described previously. The step of generating compensated signals involves creating post-compensated signals. These are signals adjusted *after* reception to cancel out crosstalk that has already occurred.
5. The method of claim 4 further comprising the step of receiving uncompensated signals in an access node of the system from respective network terminals of the system over respective ones of the channels, wherein the post-compensated signals are generated from respective ones of the received uncompensated signals.
This expands on the post-compensation method. An access node receives uncompensated signals from network terminals over the communication channels. It then generates post-compensated signals from these received signals to remove the effects of crosstalk. This correction happens at the receiving end (access node).
6. The method of claim 1 wherein the matrix representation of the crosstalk estimates is in the form of an N×N precoder or postcoder matrix, where N denotes the number of channels, and further wherein the N×N precoder or postcoder matrix is converted by a vector control entity into the compressed representation comprising the value array and the index array, each of which has N·m entries, where m is less than N and denotes a specified maximum number of dominant disturber channels for a given victim channel.
This adds detail to the crosstalk reduction method. The crosstalk estimates are represented as an N x N matrix (precoder or postcoder matrix), where N is the number of channels. A "vector control entity" compresses this matrix into the value and index arrays, each containing N * m entries. 'm' is less than 'N' and represents the maximum number of dominant interfering channels considered for each channel, thus compressing the crosstalk information.
7. The method of claim 6 wherein the entries of the value array comprise complex values corresponding to respective ones of m selected crosstalk estimates from each of N rows of the precoder or postcoder matrix.
Building on the method where crosstalk is represented with a compressed value and index array, the "value array" entries are complex numbers. These complex values correspond to 'm' selected crosstalk estimates from each of the 'N' rows of the precoder or postcoder matrix, representing the magnitude and phase of the crosstalk.
8. The method of claim 6 wherein the entries of the index array comprise scalar values denoting indices of respective ones of m selected crosstalk estimates from each of N rows of the precoder or postcoder matrix.
Building on the method where crosstalk is represented with a compressed value and index array, the "index array" entries are scalar values. These scalar values indicate the original row and column indices of the 'm' selected crosstalk estimates within the original 'N' rows of the precoder or postcoder matrix, allowing the correct crosstalk values to be identified.
9. The method of claim 6 wherein at least one of the value array and the index array is in the form of a single row of length N·m.
In the compression of crosstalk data into value and index arrays, at least one of these arrays (either the value array or the index array) is stored as a single, long row of length N*m, simplifying memory access and data processing.
10. The method of claim 6 wherein at least one of the value array and the index array is in the form of a matrix of dimension N×m.
In the compression of crosstalk data into value and index arrays, at least one of these arrays (either the value array or the index array) is structured as a matrix with dimensions N x m. This allows for easier access to crosstalk information relating to a specific channel.
12. A non-transitory computer-readable storage medium having embodied therein executable program code that when executed by a processor of an access node of the system causes the access node to perform the steps of the method of claim 1 .
A non-transitory computer-readable storage medium (e.g., hard drive, flash drive) stores program code. When a processor in an access node executes this code, the access node performs the crosstalk reduction method: 1) Measure crosstalk. 2) Generate a compressed representation (value and index arrays). 3) Generate compensated signals based on this compressed representation.
13. An apparatus comprising: an access node configured to control crosstalk between channels of communication system; wherein the access node comprises: a plurality of transceivers; and vectoring circuitry coupled to the transceivers; the vectoring circuitry comprising a processor coupled to a memory and being operative to estimate crosstalk between the channels of the system, to generate a compressed representation of the crosstalk estimates, and to generate compensated signals based on the compressed representation of the crosstalk estimates; wherein the compressed representation comprises a value array and an index array, the value array comprising selected values from each of a plurality of rows of a matrix representation of the crosstalk estimates and the index array identifying locations of the selected values in the matrix representation of the crosstalk estimates.
An apparatus (device) designed to reduce crosstalk in a communication system. It includes an access node with transceivers and "vectoring circuitry". This circuitry: 1) Measures crosstalk between channels. 2) Creates a compressed representation of the crosstalk (value and index arrays, containing selected values and their locations within a crosstalk matrix). 3) Generates compensated signals based on this compressed representation to counteract interference.
14. The apparatus of claim 13 wherein the access node comprises a DSL access multiplexer.
The crosstalk-reducing apparatus described previously uses a DSL access multiplexer (DSLAM) as the access node. The DSLAM contains the transceivers and vectoring circuitry needed for crosstalk cancellation.
15. The apparatus of claim 13 wherein the vectoring circuitry comprises: a vector control entity operative to estimate the crosstalk between the channels of the system and to generate the compressed representation of the crosstalk estimates; and a vectoring signal processing module operative to generate the compensated signals based on the compressed representation of the crosstalk estimates.
In the crosstalk-reducing apparatus, the vectoring circuitry is further divided into two modules: a "vector control entity" that estimates the crosstalk and creates the compressed representation (value and index arrays), and a "vectoring signal processing module" that uses the compressed representation to generate the compensated signals.
16. The apparatus of claim 13 wherein the processor comprises a vector processor configured to generate the compensated signals.
The crosstalk-reducing apparatus includes a vector processor. The vector processor is used to generate the compensated signals.
17. The apparatus of claim 16 wherein the vector processor comprises: a plurality of computation slices arranged in parallel with one another, one for each of the channels; wherein each of the computation slices comprises: first memory circuitry for storing entries of the index array; second memory circuitry for storing entries of the value array; third memory circuitry for storing entries of an uncompensated input signal vector and having a selection input coupled to an output of the first memory circuitry; a complex multiply-accumulate unit having inputs coupled to outputs of the first and third memory circuitry; and an output register having an input coupled to an output of the complex multiply-accumulate unit; the computation slice generating entries of a compensated output signal vector.
The vector processor, used to generate compensated signals for crosstalk reduction, contains multiple "computation slices". Each slice is dedicated to one channel. Each slice contains: 1) Memory to store the "index array" entries. 2) Memory to store the "value array" entries. 3) Memory for the uncompensated input signal, with the selection of this memory controlled by the index array. 4) A complex multiply-accumulate unit that multiplies selected input signal values by crosstalk values. 5) An output register that holds the resulting compensated signal value.
18. The apparatus of claim 17 wherein the compressed representation is stored in an external memory of the vector processor under control of a vector control entity and portions of said representation are supplied to the first and second memory circuitry of the vector processor as needed for vectoring computations performed by the vector processor.
In the vector processor, the compressed crosstalk representation (value and index arrays) is stored in external memory. The vector control entity manages the transfer of relevant portions of these arrays to the internal memory of each computation slice as needed for the vectoring calculations.
19. The apparatus of claim 17 wherein the vector processor is implemented in the form of a single integrated circuit.
The vector processor described above, with its parallel computation slices and memory elements, is implemented as a single integrated circuit (chip).
20. A communication system comprising the apparatus of claim 13 .
A complete communication system that incorporates the crosstalk-reducing apparatus described previously.
21. An integrated circuit comprising: a vector processor operative to generate compensated signals based on a compressed representation of estimates of crosstalk between channels of a communication system; wherein the compressed representation comprises a value array and an index array, the value array comprising selected values from each of a plurality of rows of a matrix representation of the crosstalk estimates and the index array identifying locations of the selected values in the matrix representation of the crosstalk; wherein the vector processor comprises: a plurality of computation slices arranged in parallel with one another, one for each of the channels; wherein each of the computation slices comprises: first memory circuitry for storing entries of the index array; second memory circuitry for storing entries of the value array; third memory circuitry for storing entries of an uncompensated input signal vector and having a selection input coupled to an output of the first memory circuitry; a complex multiply-accumulate unit having inputs coupled to outputs of the first and third memory circuitry; and an output register having an input coupled to an output of the complex multiply-accumulate unit; the computation slice generating entries of a compensated output signal vector.
An integrated circuit (chip) containing a vector processor for generating compensated signals to reduce crosstalk. It uses a compressed representation of the crosstalk (value and index arrays, containing selected values and their locations in the crosstalk matrix). The vector processor has multiple parallel "computation slices," one for each channel. Each slice contains: 1) Index array memory. 2) Value array memory. 3) Input signal memory (selection controlled by the index array). 4) A complex multiply-accumulate unit. 5) An output register. This slice computes an entry of the compensated output signal vector.
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October 29, 2010
August 20, 2013
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