A computer-implemented method to debug testbench code of a testbench associated with a circuit design by recording a trace of call frames along with activities of the circuit design. By correlating and displaying the recorded trace of call frames, the method enables users to easily trace an execution history of subroutines executed by the testbench thereby to debug the testbench code. In addition, users can trace source code of the testbench code by using the recorded trace of call frames. Furthermore, users can debug the testbench code utilizing a virtual simulation, which is done by post-processing records of the virtual simulation stored in a database.
Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A computer-implemented method for recording a trace of call frames during a simulation of a circuit design with a testbench, wherein the testbench comprises a plurality of subroutines, wherein each subroutine of the plurality of subroutines comprises a code section, the method comprising using a computer to perform steps of: (a) for each subroutine of the plurality of subroutines, providing a first call-back routine which is called before the code section of the subroutine is executed; (b) starting the simulation of the circuit design with the testbench; (c) for each subroutine of plurality of subroutines, recording a first simulation time at which a corresponding first call-back routine of the subroutine is executed, a first tag indicating a beginning of the subroutine, and a first subroutine ID to identify the subroutine in a beginning call frame when the corresponding first call-back routine is called, and wherein the trace of call frames is formed according to an order of the call-back routines that are called one by one during an execution of the testbench at their respective simulation times.
The invention is a method to record a log of subroutine calls during a circuit simulation for debugging purposes. The circuit simulation uses a testbench composed of multiple subroutines. For each subroutine, a "first call-back routine" is executed just *before* the subroutine's code runs. The method starts the simulation and, upon executing a "first call-back routine," records the simulation time, a tag indicating the subroutine's start, and a unique subroutine ID into a "beginning call frame." The order of these recorded call frames represents the execution history of the testbench during simulation.
2. The computer-implemented method according to claim 1 , wherein the step (a) a further comprises a sub-step of: (a1) for each subroutine of plurality of subroutines, providing a second call-back routine which is called after the code section of the subroutine is executed; and wherein the step (c) further comprises a sub-step of: (c1) for each subroutine of plurality of subroutines, recording a second simulation time at which a corresponding second call-back routine of the subroutine is executed, a second tag indicating an ending of the subroutine, and a second subroutine ID to identify the subroutine in an ending call frame when the corresponding second call-back routine is called.
This builds on the previous method of recording subroutine calls. Now, in addition to the "first call-back routine" executed *before* each subroutine, a "second call-back routine" is executed *after* the subroutine code runs. When this "second call-back routine" is executed, the method records the simulation time, a tag indicating the subroutine's end, and a unique subroutine ID into an "ending call frame." This provides both start and end markers for each subroutine's execution in the call frame trace.
3. The computer-implemented method according to claim 2 , wherein the testbench is written in SystemVerilog language and comprises a plurality of classes, wherein each of the plurality of classes comprises a plurality of variables and at least one method; and wherein the plurality of subroutines comprises the methods associated with the plurality of classes.
Expanding on the prior method, the testbench is written in SystemVerilog, using classes that contain variables and methods (the methods are the subroutines being tracked). The "first call-back routine" is called before each method of the class, and the "second call-back routine" is called after each method of the class. This creates detailed trace data showing when each SystemVerilog class method is entered and exited during the simulation.
4. The computer-implemented method according to claim 3 , wherein the step (c) further comprises recording a first variable status of a class of the subroutine in the beginning call frame when the corresponding first call-back routine is called.
In addition to the previous method for SystemVerilog testbenches, when the "first call-back routine" is called (at the *beginning* of a method), the current values of the class variables are also recorded in the "beginning call frame" along with the time, start tag, and subroutine ID. This captures the state of the SystemVerilog class at the entry point of each method.
5. The computer-implemented method according to claim 4 , wherein the step (c1) further comprises recording a second variable status of the class of the subroutine in the ending call frame when the corresponding second call-back routine is called.
Building on the previous claim, when the "second call-back routine" is called (at the *end* of a method), the current values of the class variables are recorded in the "ending call frame" along with the time, end tag, and subroutine ID. This captures the state of the SystemVerilog class at the exit point of each method. The combination of Claims 4 and 5 allows developers to understand exactly how values are modified during a method call.
6. The computer-implemented method according to claim 3 , wherein an invocation of the first call-back routine is provided by adding a call statement to call the first call-back routine at the beginning of each corresponding method of the class in the step (a).
Referring back to the SystemVerilog testbench method, the "first call-back routine" is triggered by simply adding a statement to call the "first call-back routine" at the very beginning of each method in the class. This is how the recording mechanism is hooked into the SystemVerilog code.
7. The computer-implemented method according to claim 3 , wherein the invocation of the second call-back routine is provided by adding a call statement to call the second call-back routine at the end of each corresponding method of the class in the step (a1).
Similar to the previous claim, the "second call-back routine" is triggered by adding a statement to call the "second call-back routine" at the very end of each method in the class. This completes the hook for tracing entry and exit of SystemVerilog methods.
8. The computer-implemented method according to claim 3 , wherein each of the simulation times is obtained through programming language interface (PLI) of Verilog.
When recording the simulation times in the SystemVerilog testbench method, the times are obtained using the Programming Language Interface (PLI) of Verilog. PLI provides the interface between Verilog simulation and the C/C++ routines, thus enabling C/C++ to interact and extract data from the simulation.
9. The computer-implemented method according to claim 2 , wherein the step (c) further comprises recording a caller-subroutine ID to identify a caller subroutine that calls the subroutine and a position at which the subroutine is called in the beginning call frame when the corresponding first call-back routine is called.
Expanding on the base method, when the "first call-back routine" is triggered, the method also records the ID of the *calling* subroutine (the subroutine that called the current subroutine) and the line of code where the call occurred. This information is added to the "beginning call frame", enabling call stack reconstruction.
10. The computer-implemented method according to claim 9 , wherein the step (c1) further comprises identifying the corresponding beginning call frame of the ending call frame by searching back the call frames until a first matched call frame is found, wherein the first matched call frame has a tag to indicate a beginning of a subroutine, and the first subroutine ID recorded in the first matched call frame is the same as the second subroutine ID recorded in the ending call frame; and recording in the ending call frame the same caller-subroutine ID, and position at which the subroutine is called, as recorded in the first matched call frame.
Expanding on the previous method that records the caller subroutine ID, when creating an "ending call frame," the method finds the corresponding "beginning call frame" by searching backwards through the call frame log until it finds a frame with a "beginning" tag and a subroutine ID that matches the ID in the ending call frame. It then copies the caller subroutine ID and call position from the matching "beginning call frame" into the "ending call frame."
11. The computer-implemented method according to claim 2 , further comprising a step of: (d) replaying the simulation according to a plurality of value change data associated with the call frames recorded in a database without actually running the simulation of the circuit design with the testbench.
Building on the method that records start and end of subroutines, after recording the call frames during simulation, the method allows "replaying" the simulation using the recorded data *without* actually re-running the simulation. The method leverages recorded value changes stored with the call frames in a database.
12. The computer-implemented method according to claim 11 , wherein the step (d) further comprises generating a graphic window to display a waveform of a plurality of value change data for a simulation time period according to the plurality of value change data recorded in the database.
Building on the "replay" feature, the method generates a graphical window that displays waveforms representing value changes over a specified simulation time period, based on the data recorded during the initial simulation and stored in the database.
13. The computer-implemented method according to claim 12 , wherein the graphic window comprises an activation annotation to display the corresponding call frames recorded at a specified simulation time within the simulation time period.
Expanding on the waveform display, the graphical window also includes "activation annotations" that show the corresponding call frames recorded at specific simulation times within the displayed waveform. This connects the value changes directly to the subroutine calls.
14. The computer-implemented method according to claim 13 , wherein the graphic window comprises an activation annotation to display a source file of the subroutine for the corresponding call frame recorded at the specified simulation time.
In addition to displaying call frames, the "activation annotation" in the graphical window can also display the source code file of the subroutine associated with the selected call frame, allowing the developer to see the code being executed at that point in the simulation.
15. The computer-implemented method according to claim 14 , wherein the graphic window comprises an activation annotation to single step through the subroutine while viewing the source file of the subroutine.
Expanding on the source code display, the method allows the user to "single step" through the subroutine code displayed in the graphical window, while still viewing the source file. This enables detailed debugging of the subroutine's execution.
16. The computer-implemented method according to claim 13 , wherein the graphic window comprises an activation annotation to display a source file of the caller subroutine for a subroutine associated with a first call frame recorded at the specified simulation time according to the caller-subroutine ID and the position at which the subroutine is called in the first call frame.
Instead of showing the source code of the *current* subroutine, the activation annotation can display the source code of the *calling* subroutine (the subroutine that called the current one), using the caller subroutine ID and call position recorded in the first call frame. This allows the developer to trace the call stack upwards.
17. The computer-implemented method according to claim 13 , further comprising a step of: (e) setting a breakpoint and generating the graphic window containing the breakpoint according to the plurality of value change data and the call frames recorded in the database without running the simulation of the circuit design with the testbench.
The method also enables setting breakpoints within the recorded simulation data. A user sets a breakpoint, and the graphic window is generated based on the pre-recorded value change data and call frames. Critically, this all happens *without* needing to re-run the simulation, enabling rapid breakpoint analysis.
18. The computer-implemented method according to claim 2 , wherein the testbench is written in SystemVerilog; and wherein the plurality of call-back routines comprises a plurality of C (C++) functions, and the plurality of C (C++) functions are called from the SystemVerilog simulation kernel through programming language interface (PLI) of Verilog.
In this variation, the testbench is written in SystemVerilog, and the "first" and "second" call-back routines are implemented as C/C++ functions. These C/C++ functions are called from the SystemVerilog simulation kernel using the Verilog Programming Language Interface (PLI).
19. The computer-implemented method according to claim 18 , wherein the first and second call-back routines are provided by registering the call-back routines through programming language interface (PLI) of Verilog in the step (a) and step (c), respectively.
In the previous method, the registration of the C/C++ call-back routines (to be called before and after the subroutines) is done through the Verilog PLI.
20. The computer-implemented method according to claim 2 , wherein the step (c) further comprises recording an index of a call frame in the beginning call frame when the corresponding first call-back routine is called.
In addition to recording simulation time and subroutine ID, the "beginning call frame" also stores an index representing its position within the call frame sequence.
21. The computer-implemented method according to claim 20 , wherein the step (c1) further comprises recording the index associated with the beginning call frame in the ending call frame when the corresponding second call-back routine is called.
When creating the "ending call frame," the method also records the index of the corresponding "beginning call frame," linking the two frames directly together.
22. A computer-implemented method for debugging a testbench, wherein the testbench comprises a plurality of subroutines, the method comprising using a computer to perform steps of: (a) providing and executing a recording routine to log trace data for each subroutine of the plurality of subroutines, which are to be executed one by one, at their respective simulation times while running a simulation with the testbench; and (b) replaying executions of the plurality of subroutines using the logged trace data recorded at the simulation times without rerunning the simulation.
The invention is a method to debug a testbench by recording execution traces for each subroutine at their simulation times and then replaying the subroutine executions from the logged data without re-running the simulation. A "recording routine" logs trace data while the simulation runs. Later, the execution of the subroutines is replayed using the logged trace data, allowing for debugging without repeating the simulation.
23. The computer-implemented method according to claim 22 , wherein the testbench is written in SystemVerilog language and comprises a plurality of classes, wherein each of the plurality of classes comprises a plurality of variables and at least one method; and wherein the plurality of subroutines comprises the methods associated with the plurality of classes.
The method of the previous claim, where the testbench is written in SystemVerilog using classes that contain variables and methods (the methods are the subroutines being tracked). This allows replaying the simulation of the SystemVerilog testbench and debugging its execution based on pre-recorded trace data, without actually re-running the simulation.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
May 8, 2011
August 27, 2013
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