A variable resistance memory device comprises a memory cell comprising a variable resistance device and a select transistor connected in series to the variable resistance device. The variable resistance memory device further comprises a write driver for supplying a write voltage to opposite sides of the memory cell, and a feedback circuit for detecting a resistance change of the variable resistance device and controlling a gate voltage of the select transistor according to the detected resistance change.
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1. A variable resistance memory device, comprising: a memory cell comprising a variable resistance device and a select transistor connected in series with the variable resistance device; a write driver that generates a write voltage across the memory cell during a write operation of the variable resistance device; and a feedback circuit that detects a resistance change of the variable resistance device during the write operation and controls a gate voltage of the select transistor during the write operation according to the detected resistance change.
A variable resistance memory device contains a memory cell. This memory cell includes a variable resistance device (a resistor that can change its resistance) and a select transistor connected in series. A write driver supplies a write voltage across the memory cell during write operations, changing the resistance of the variable resistance device. A feedback circuit detects this resistance change during the write operation and adjusts the gate voltage of the select transistor based on the detected change. This allows for precise control during writing.
2. The variable resistance memory device of claim 1 , wherein the variable resistance device comprises a bipolar resistance memory material.
The variable resistance memory device as described above uses a *bipolar* resistance memory material as its variable resistance device. That is, the resistor changes its resistance based on the direction of current flow. The overall device contains a memory cell with this bipolar variable resistor and a select transistor connected in series. A write driver supplies a write voltage to the memory cell during a write operation, and a feedback circuit detects resistance changes of the bipolar resistor and adjusts the select transistor's gate voltage accordingly.
3. The variable resistance memory device of claim 1 , wherein the select transistor comprises a negative metal oxide semiconductor (NMOS) transistor.
The variable resistance memory device as described above uses an NMOS (Negative Metal Oxide Semiconductor) transistor as its select transistor. That is, the transistor that controls current flow through the memory cell is an NMOS. The overall device contains a memory cell with a variable resistor and this NMOS transistor connected in series. A write driver supplies a write voltage to the memory cell during a write operation, and a feedback circuit detects resistance changes of the variable resistor and adjusts the NMOS transistor's gate voltage accordingly.
4. The variable resistance memory device of claim 1 , wherein, during a reset program operation, the write driver provides a reset voltage to a first side of the memory cell adjacent to the variable resistance device, and grounds a second side of the memory cell adjacent to the select transistor.
The variable resistance memory device described above, when performing a reset operation, involves the write driver applying a reset voltage to the side of the memory cell connected to the variable resistance device, while the opposite side of the memory cell (connected to the select transistor) is grounded. This reset operation brings the variable resistor to a consistent starting point. The device contains the memory cell with the variable resistor and a select transistor connected in series. The feedback circuit still detects changes in the variable resistor's resistance and controls the select transistor gate.
5. The variable resistance memory device of claim 4 , wherein, during a set program operation, the write driver grounds the first side and provides a set voltage to the second side.
The variable resistance memory device, in a "set" operation (opposite of reset above), involves the write driver grounding the side of the memory cell connected to the variable resistance device and applying a set voltage to the side connected to the select transistor. This is opposite from how the device sets the "reset" state described above which has the write driver providing a reset voltage to the side of the memory cell adjacent to the variable resistance device, and grounding the second side of the memory cell adjacent to the select transistor. The device has the memory cell including the variable resistance device and select transistor connected in series with the feedback circuit still monitoring the resistance change and controlling the select transistor.
6. The variable resistance memory device of claim 1 , wherein the feedback circuit detects the resistance change by sensing a change in a node voltage apparent on a node located between the variable resistance device and the select transistor.
The variable resistance memory device described previously detects the resistance change by sensing the voltage change at the node (connection point) between the variable resistance device and the select transistor. The feedback circuit monitors the voltage at this point to determine if the resistance has changed sufficiently. This provides a direct feedback signal from the variable resistor itself. The device still contains the memory cell with the variable resistor and a select transistor connected in series along with the write driver providing the write voltage.
7. The variable resistance memory device of claim 6 , wherein the feedback circuit transfers a wordline voltage to a gate of the select transistor where the node voltage is greater than a reference voltage.
Building on the previous description, the variable resistance memory device's feedback circuit transfers a "wordline voltage" (a control signal used to activate the memory cell) to the *gate* of the select transistor IF the voltage at the node between the variable resistor and the select transistor is *higher* than a specific reference voltage. The device still contains the memory cell with the variable resistor and a select transistor connected in series along with the write driver providing the write voltage and the feedback circuit detecting the change by sensing the node voltage.
8. The variable resistance memory device of claim 7 , wherein the feedback circuit transfers the node voltage to the gate of the select transistor where the node voltage is less than or equal to the reference voltage.
Further expanding on the variable resistance memory device's behavior, the feedback circuit transfers the *node voltage itself* (the voltage between the variable resistor and the select transistor) to the *gate* of the select transistor IF the node voltage is *less than or equal to* a specific reference voltage. This is complementary to the prior claim. The device still contains the memory cell with the variable resistor and a select transistor connected in series along with the write driver providing the write voltage and the feedback circuit detecting the change by sensing the node voltage. The device also transfers a wordline voltage to a gate of the select transistor where the node voltage is greater than a reference voltage, as described in the previous claim.
9. The variable resistance memory device of claim 1 , wherein the feedback circuit comprises a pass transistor that provides a node voltage apparent at a node between the variable resistance device and the select transistor to a gate of the select transistor in response to a wordline voltage.
The variable resistance memory device's feedback circuit uses a "pass transistor." This pass transistor connects the node voltage (between the variable resistance device and the select transistor) to the gate of the select transistor, but *only* when a "wordline voltage" signal is active. In effect, the wordline voltage enables the path for the node voltage to influence the select transistor's behavior. The device still contains the memory cell with the variable resistor and a select transistor connected in series along with the write driver providing the write voltage.
10. The variable resistance memory device of claim 9 , wherein the wordline voltage is provided to a gate of the pass transistor.
In the variable resistance memory device, the "wordline voltage" described above, which controls the pass transistor in the feedback circuit, is applied directly to the *gate* of that pass transistor. Therefore, the wordline signal directly enables or disables the pass transistor's ability to transmit the node voltage to the select transistor's gate. The pass transistor is what provides a node voltage apparent at a node between the variable resistance device and the select transistor to a gate of the select transistor in response to a wordline voltage. The device has the memory cell, write driver, feedback circuit, etc., as described above.
11. The variable resistance memory device of claim 10 , wherein the pass transistor transfers the reference voltage to the gate of the select transistor where the node voltage is greater than a reference voltage.
In the variable resistance memory device, the pass transistor within the feedback circuit transfers a reference voltage to the gate of the select transistor if the node voltage is greater than a reference voltage. As stated in the previous claim, the wordline voltage is provided to a gate of the pass transistor. The pass transistor provides a node voltage apparent at a node between the variable resistance device and the select transistor to a gate of the select transistor in response to a wordline voltage. The device has the memory cell, write driver, feedback circuit, etc., as described above.
12. The variable resistance memory device of claim 11 , wherein the pass transistor transfers the node voltage to a gate of the select transistor where the node voltage is less than or equal to the reference voltage.
Continuing with the feedback circuit details of the variable resistance memory device, the pass transistor will transfer the *node voltage* itself to the gate of the select transistor if the node voltage is *less than or equal to* a reference voltage. This behavior is in contrast to where the pass transistor transfers the reference voltage to the gate of the select transistor where the node voltage is greater than a reference voltage. Also, a wordline voltage is provided to a gate of the pass transistor, which provides a node voltage apparent at a node between the variable resistance device and the select transistor to a gate of the select transistor in response to the wordline voltage. The device still has the memory cell, write driver, etc., as described above.
13. The variable resistance memory device of claim 11 , wherein the reference voltage has a magnitude equal to a magnitude of the wordline voltage minus a threshold voltage of the pass transistor.
The reference voltage used by the feedback circuit in the variable resistance memory device has a specific value: it's equal to the wordline voltage *minus* the threshold voltage of the pass transistor itself. This ensures proper switching behavior of the pass transistor. The pass transistor transfers the reference voltage to the gate of the select transistor if the node voltage is greater than a reference voltage, where the wordline voltage is provided to a gate of the pass transistor, which provides a node voltage apparent at a node between the variable resistance device and the select transistor to a gate of the select transistor in response to the wordline voltage. The device still has the memory cell, write driver, etc., as described above.
14. The variable resistance memory device of claim 13 , wherein the feedback circuit further comprises a pull of transistor that grounds the gate of the select transistor where the wordline is inactivated.
The variable resistance memory device's feedback circuit *also* includes a "pull-down transistor." This transistor grounds the gate of the select transistor when the wordline signal is *inactive* (meaning the memory cell is not being accessed). This ensures the select transistor is turned OFF when not in use. The reference voltage has a magnitude equal to a magnitude of the wordline voltage minus a threshold voltage of the pass transistor, and the pass transistor transfers the reference voltage to the gate of the select transistor if the node voltage is greater than a reference voltage, where the wordline voltage is provided to a gate of the pass transistor, which provides a node voltage apparent at a node between the variable resistance device and the select transistor to a gate of the select transistor in response to the wordline voltage. The device still has the memory cell, write driver, etc., as described above.
15. A method of performing a write operation of a variable resistance memory device comprising a memory cell comprising a variable resistance device and a select transistor connected in series with the variable resistance device, the method comprising: applying a write voltage across the memory cell; detecting whether a node voltage apparent at a node between the variable resistance device and the select transistor has reached a reference voltage while the write voltage is applied across the memory cell; and transferring the node voltage to a gate of the select transistor upon detecting that the distribution voltage is less than or equal to the reference voltage.
A method for writing to a variable resistance memory device (which contains a variable resistance device and a select transistor in series) involves applying a write voltage across the memory cell. While the write voltage is applied, the method detects if the voltage at the node between the variable resistance device and the select transistor has reached a specific reference voltage. If the node voltage is less than or equal to this reference voltage, then the method transfers the node voltage *itself* to the gate of the select transistor.
16. The writing method of claim 15 , wherein the reference is transferred to the gate of the select transistor where the node voltage is greater than the reference voltage.
In the described method for writing to a variable resistance memory device, if the node voltage (the voltage between the variable resistance device and select transistor) is *greater* than the reference voltage, then the *reference voltage itself* is transferred to the gate of the select transistor. This is in contrast to transferring the node voltage to a gate of the select transistor upon detecting that the distribution voltage is less than or equal to the reference voltage. The overall writing process involves applying a write voltage across the memory cell and detecting whether a node voltage has reached a reference voltage while the write voltage is applied.
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February 14, 2011
September 3, 2013
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