A variable resistance memory device comprises a memory cell comprising a variable resistance device and a select transistor connected in series to the variable resistance device. The variable resistance memory device further comprises a write driver for supplying a write voltage to opposite sides of the memory cell, and a feedback circuit for detecting a resistance change of the variable resistance device and controlling a gate voltage of the select transistor according to the detected resistance change.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A variable resistance memory device, comprising: a memory cell comprising a variable resistance device and a select transistor connected in series with the variable resistance device; a write driver that generates a write voltage across the memory cell during a write operation of the variable resistance device; and a feedback circuit that detects a resistance change of the variable resistance device during the write operation and controls a gate voltage of the select transistor during the write operation according to the detected resistance change.
2. The variable resistance memory device of claim 1 , wherein the variable resistance device comprises a bipolar resistance memory material.
3. The variable resistance memory device of claim 1 , wherein the select transistor comprises a negative metal oxide semiconductor (NMOS) transistor.
4. The variable resistance memory device of claim 1 , wherein, during a reset program operation, the write driver provides a reset voltage to a first side of the memory cell adjacent to the variable resistance device, and grounds a second side of the memory cell adjacent to the select transistor.
5. The variable resistance memory device of claim 4 , wherein, during a set program operation, the write driver grounds the first side and provides a set voltage to the second side.
6. The variable resistance memory device of claim 1 , wherein the feedback circuit detects the resistance change by sensing a change in a node voltage apparent on a node located between the variable resistance device and the select transistor.
7. The variable resistance memory device of claim 6 , wherein the feedback circuit transfers a wordline voltage to a gate of the select transistor where the node voltage is greater than a reference voltage.
8. The variable resistance memory device of claim 7 , wherein the feedback circuit transfers the node voltage to the gate of the select transistor where the node voltage is less than or equal to the reference voltage.
9. The variable resistance memory device of claim 1 , wherein the feedback circuit comprises a pass transistor that provides a node voltage apparent at a node between the variable resistance device and the select transistor to a gate of the select transistor in response to a wordline voltage.
10. The variable resistance memory device of claim 9 , wherein the wordline voltage is provided to a gate of the pass transistor.
11. The variable resistance memory device of claim 10 , wherein the pass transistor transfers the reference voltage to the gate of the select transistor where the node voltage is greater than a reference voltage.
12. The variable resistance memory device of claim 11 , wherein the pass transistor transfers the node voltage to a gate of the select transistor where the node voltage is less than or equal to the reference voltage.
13. The variable resistance memory device of claim 11 , wherein the reference voltage has a magnitude equal to a magnitude of the wordline voltage minus a threshold voltage of the pass transistor.
14. The variable resistance memory device of claim 13 , wherein the feedback circuit further comprises a pull of transistor that grounds the gate of the select transistor where the wordline is inactivated.
15. A method of performing a write operation of a variable resistance memory device comprising a memory cell comprising a variable resistance device and a select transistor connected in series with the variable resistance device, the method comprising: applying a write voltage across the memory cell; detecting whether a node voltage apparent at a node between the variable resistance device and the select transistor has reached a reference voltage while the write voltage is applied across the memory cell; and transferring the node voltage to a gate of the select transistor upon detecting that the distribution voltage is less than or equal to the reference voltage.
16. The writing method of claim 15 , wherein the reference is transferred to the gate of the select transistor where the node voltage is greater than the reference voltage.
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February 14, 2011
September 3, 2013
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