A system for increasing the efficiency of data transfer through a serializer-deserializer (SerDes) link, and for reducing data latency caused by differences between arrival times of the data on the SerDes link and the system clock with which the device operates.
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1. A method for reducing data latency during deserialization of one or more lanes of serial data, the method comprising: (a) providing a double buffer having an upper buffer half and a lower buffer half, (b) sequentially writing pairs of deserialized bits of the serial data to the upper buffer half at a first clock speed of a first clock signal, (c) when the upper buffer half is full, reading all data from the upper buffer half in parallel into a physical coding sublayer at a second clock speed of a system clock signal, wherein the second clock speed is less than and dependent on the first clock speed, (d) sequentially writing pairs of deserialized bits of the serial data to the lower buffer half at the first clock speed, (e) when the lower buffer half is full, reading all data from the lower buffer half in parallel into the physical coding sublayer at the second clock speed, and (f) aligning the data from the upper buffer half and the lower buffer half in the physical coding sublayer.
A method to reduce latency when converting serial data to parallel data. A double buffer is used, with an upper and lower half. Pairs of bits from the serial data are written sequentially into the upper half of the buffer using a fast clock. When the upper half is full, all data in the upper half is read out in parallel into a physical coding sublayer using a slower system clock. Then, pairs of bits are written to the lower buffer half using the fast clock. When the lower half is full, its data is read out in parallel into the physical coding sublayer using the slower system clock. Finally, the data from both buffer halves are aligned in the physical coding sublayer.
2. The method of claim 1 further comprising, prior to step (b), registering a first bit of the serial data on a leading clock edge of the first clock signal, and registering a second bit of the serial data on a trailing clock edge of the first clock signal, thereby forming a pair of deserialized bits.
The method for reducing data latency from the previous description also registers each bit of the serial data on both the rising and falling edge of the fast clock signal. The first bit of serial data is registered on the rising clock edge, and the second bit of serial data is registered on the falling clock edge. This creates pairs of deserialized bits for subsequent writing into the double buffer.
3. The method of claim 1 wherein the upper buffer half and the lower buffer half each comprise ten registers configured in pairs.
In the method for reducing data latency using a double buffer, both the upper and lower halves of the double buffer consist of ten registers configured as five pairs. This structure provides storage for deserialized data before it is read out in parallel.
4. The method of claim 1 further comprising the step of performing training to synchronize the writing of the pairs of deserialized bits of the serial data at the first clock speed and the reading of the data from the upper and lower buffer halves at the second clock speed.
The data latency reduction method using a double buffer includes a training step. This training synchronizes the writing of pairs of deserialized bits at the faster clock speed with the reading of data from the buffer halves at the slower system clock speed. This ensures data integrity and efficient transfer.
5. The method of claim 1 wherein the system clock signal is a divided version of the first clock signal.
The method for reducing data latency using a double buffer where the system clock signal used to read data from the buffer is derived by dividing the frequency of the faster clock signal used to write data into the buffer.
6. The method of claim 5 , further comprising aligning the system clock signal to a slowest lane of the multilane serial data.
In the method for reducing data latency where the system clock is derived from the faster clock, the system clock signal is aligned to the slowest lane of a multi-lane serial data stream. This synchronization accounts for variations in signal arrival times across different lanes.
7. The method of claim 1 , further comprising: activating a system reset signal to initialize the double buffer; registering the system reset signal in response to the system clock signal, thereby providing a first registered system reset signal; and then registering the first registered system reset signal in response to the first clock signal, thereby providing a second registered system reset signal.
The data latency reduction method also involves a reset sequence. A system reset signal initializes the double buffer. This reset signal is registered using the slower system clock, creating a first registered reset signal. This first signal is then registered again using the faster clock, creating a second registered reset signal.
8. The method of claim 7 , wherein the steps of reading data from the upper buffer half and reading data from the lower buffer half are initialized in response to activating the system reset signal.
In the method that uses a reset sequence to initialize the double buffer, the reading of data from both the upper and lower buffer halves is triggered by activating the initial system reset signal. This ensures a clean start for data transfer.
9. The method of claim 8 , wherein the steps of writing pairs of deserialized bits of the serial data to the upper buffer half and the lower buffer half are initialized by the second registered system reset signal.
In the method with the reset sequence, the writing of pairs of deserialized bits into both the upper and lower buffer halves is initiated by the *second* registered system reset signal, which is clocked by the faster clock.
10. The method of claim 7 , further comprising: writing pairs of deserialized bits of the serial data to a same register of the upper buffer half or the lower buffer half for two consecutive cycles of the first clock signal; and then cyclically writing pairs of deserialized bits of the serial data to a plurality of registers of the upper buffer half and the lower buffer half for subsequent cycles of the first clock signal.
In the method with the reset sequence, during initialization, pairs of deserialized bits are written to the *same* register in the upper or lower buffer half for two consecutive cycles of the fast clock. After this, the pairs of bits are cyclically written to the plurality of registers in the upper and lower buffer halves for the following clock cycles.
11. The method of claim 1 , further comprising: generating a first set of enable signals, wherein each of the enable signals of the first set enables a write operation to a corresponding register in the upper buffer half; and controlling the first set of enable signals to enable sequential write operations to the same register in the upper buffer half.
The method for reducing latency involves generating a set of enable signals for the upper buffer half. Each enable signal corresponds to a register within the upper buffer, enabling write operations to that specific register. These enable signals are controlled to enable sequential write operations to the *same* register within the upper buffer half.
12. The method of claim 11 , further comprising: generating a second set of enable signals, wherein each of the enable signals of the second set enables a write operation to a corresponding register in the lower buffer half; and controlling the second set of enable signals to enable sequential write operations to the same register in the lower buffer half.
The data latency reduction method from the previous description generates a second set of enable signals for the *lower* buffer half. Each signal controls write operations to a corresponding register in the lower buffer. The enable signals are controlled to enable sequential write operations to the *same* register in the lower buffer half.
13. The method of claim 11 , further comprising selecting either the upper buffer half or the lower buffer half to be read in response to the system clock signal, independent of the first set of enable signals.
In the data latency reduction method, the selection of either the upper or lower buffer half for reading is determined by the slower system clock signal, independently of the enable signals used for writing. This allows the read and write operations to function asynchronously.
14. The method of claim 1 , wherein the system clock signal has no reliance upon the first clock signal.
The data latency reduction method allows for the slower system clock to operate completely independently from the faster clock that writes data into the buffer. The system clock signal is not derived from the first clock signal.
15. The method of claim 1 further comprising repeating steps (b) through (f) until all the serial data has been buffered and aligned.
The method for reducing data latency repeats the process of writing data to the buffer, reading the data from the buffer, and aligning the data until all the incoming serial data has been processed through the double buffer and aligned in the physical coding sublayer.
16. A data interface for reducing data latency during deserialization of one or more lanes of serial data, the data interface comprising: a first clock for generating a first clock signal having a first clock speed, a second clock for generating a second clock signal having a second clock speed that is less than and dependent on the first clock speed, and a double buffer having: an upper buffer half into which pairs of deserialized bits of the serial data are sequentially written at the first clock speed, and from which all stored data is read in parallel into a physical coding sublayer at the second clock speed when the upper buffer half is full, and a lower buffer half into which pairs of deserialized bits of the serial data are sequentially written at the first clock speed, and from which all stored data is read in parallel into the physical coding sublayer at the second clock speed when the lower buffer half is full, wherein the data from the upper buffer half and the lower buffer half are aligned in the physical coding sublayer.
A data interface reduces latency when converting serial data to parallel data. It includes a fast clock generating a fast clock signal, a slower clock generating a slower system clock, and a double buffer. The upper half of the double buffer stores pairs of bits from the serial data, written sequentially using the fast clock. When full, the upper half's data is read out in parallel into a physical coding sublayer using the slow system clock. The lower half mirrors this process. Finally, data from both halves are aligned in the physical coding sublayer.
17. The data interface of claim 16 wherein the upper buffer half and the lower buffer half each comprise ten registers configured in pairs.
The data interface for reducing data latency using a double buffer, the upper and lower halves of the double buffer each contain ten registers arranged as five pairs. These registers are used to hold the deserialized data before it is transmitted in parallel.
18. The data interface of claim 16 wherein the first clock signal is a divided version of a system clock signal which is aligned to a slowest lane of the one or more lanes of serial data.
The data interface for reducing data latency uses a system clock that is a divided version of the fast clock signal. The system clock signal is also aligned to the slowest lane within a multi-lane serial data transmission to account for timing variations across the different lanes.
19. A data interface for reducing data latency during deserialization of one or more lanes of serial data, the data interface comprising: means for deserializing bits of the serial data, and providing the deserialized bits at a first clock speed in response to a first clock signal; a double buffer having an upper buffer half and a lower buffer half; means for sequentially writing a first set of the deserialized bits to the upper buffer half at the first clock speed; means for sequentially writing a second set of the deserialized bits to lower buffer half at the first clock speed; means for reading the first set of the deserialized bits from the upper buffer half in parallel into a physical coding sublayer at a second clock speed of a system clock signal when the upper buffer half is full, wherein the second clock speed is less than and dependent on the first clock speed; means for reading the second set of the deserialized bits from the lower buffer half in parallel into the physical coding sublayer at the second clock speed when the lower buffer half is full; and means for aligning the first and second sets of deserialized bits in the physical coding sublayer.
A data interface to reduce latency in serial-to-parallel conversion includes: a means for deserializing bits and providing them at a fast clock speed using a first clock signal; a double buffer; means for sequentially writing deserialized bits to the upper buffer half at the fast clock speed; means for sequentially writing deserialized bits to the lower buffer half at the fast clock speed; means for reading the upper buffer half's bits in parallel into a physical coding sublayer at the slow system clock speed when full; means for reading the lower buffer half's bits in parallel into the physical coding sublayer at the slow system clock speed when full; and means for aligning the data in the physical coding sublayer. The slow clock speed is derived from the first clock.
20. The data interface of claim 19 wherein the first clock signal is a divided version of the system clock signal.
The data interface from the previous description where the fast clock signal is derived from a system clock signal using a frequency divider.
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May 9, 2012
September 3, 2013
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