A method of designing a circuit is described. In an embodiment, a physical design implementation for the circuit is created using a plurality of entities. These entities are named “genomes”. Each entity includes a portion of a functional description of the circuit that has been synthesized into a gate-level implementation. An entity is selected to facilitate the physical design implementation meeting a plurality of design constraints. Several steps (e.g., beginning with selection of an entity) of this method are repeated several times to meet the design constraints. As a consequence, the physical design implementation provides more accurate information for use in a final physical design implementation. Moreover, the physical design implementation can be created faster than prior techniques while still allowing a global view of the physical design implementation in meeting design constraints.
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1. A method of designing an integrated circuit, comprising: receiving a functional description of said integrated circuit; creating, using a computer, a physical design implementation for said integrated circuit using a plurality of synthesized entities, wherein each synthesized entity of said plurality of synthesized entities comprises a portion of said functional description of said integrated circuit that has been synthesized into a gate-level implementation; selecting synthesized entity to facilitate said physical design implementation meeting a plurality of design constraints; accessing said functional description associated with said selected synthesized entity; accessing information associated with said physical design implementation; resynthesizing said functional description associated with said selected synthesized entity into a new gate-level implementation that takes in account said information associated with said physical design implementation; and using said resynthesized entity in said physical design implementation.
A method for designing integrated circuits on a computer. The method starts by receiving a functional description of the integrated circuit. It creates a physical design implementation of the circuit using multiple "synthesized entities." Each entity represents a portion of the circuit's functional description translated into a gate-level implementation. An entity is selected to help the physical design implementation meet certain design constraints. The functional description associated with the selected entity is accessed, as is information about the current physical design implementation. The selected entity's functional description is then resynthesized into a new gate-level implementation, taking into account the physical design information. Finally, this resynthesized entity is used in the physical design implementation.
2. The method of claim 1 , wherein said resynthesizing said functional description further comprises: performing integrated circuit chip level analysis for area, timing and power constraints using aggregate characteristics of said plurality of synthesized entities; and modifying said plurality of synthesized entities using said integrated circuit chip level analysis to satisfy said design constraints.
In the integrated circuit design method of Claim 1, the resynthesizing step includes performing integrated circuit chip-level analysis for area, timing, and power constraints, using aggregate characteristics of the synthesized entities. The synthesized entities are then modified using this chip-level analysis to satisfy the design constraints. This modification ensures that the overall design meets performance targets for size, speed, and power consumption by adjusting the individual entities. This integrated analysis and modification loop is central to refining the circuit design.
3. The method of claim 1 further comprising: if said design constraints are met, generating a gate-level implementation of said physical design implementation and using said gate-level implementation and physical design information of said physical design implementation to perform place and route operations for a final physical design implementation for said integrated circuit.
The integrated circuit design method of Claim 1 continues by checking if the design constraints are met after resynthesizing and integrating an entity. If the design constraints are met, a gate-level implementation of the current physical design implementation is generated. This gate-level implementation, combined with physical design information, is then used to perform place and route operations. These operations help create a final physical design implementation ready for manufacturing. In other words, when the design is satisfactory, it proceeds to the detailed physical layout stage.
4. The method of claim 1 , wherein said creating, selecting, accessing functional description, accessing information, resynthesizing, and using facilitate validating that said design constraints can be met for enabling development of prototypes faster than without use of said synthesized entities.
In the integrated circuit design method of Claim 1, the process of creating synthesized entities, selecting entities, accessing functional descriptions and physical design information, resynthesizing, and integrating them into the physical design implementation, helps in quickly validating whether the design constraints can be met. This approach enables faster prototyping compared to traditional methods that don't use these synthesized entities. This validation step significantly speeds up the initial design phase.
5. The method of claim 1 further comprising: if said design constraints are met, using physical design information of said physical design implementation to perform floorplan operations for a final physical design implementation for said integrated circuit.
The integrated circuit design method of Claim 1 involves using physical design information from the current physical design implementation to perform floorplanning operations for a final physical design implementation, provided the design constraints are met. This means that once a satisfactory physical design is achieved, the method uses that design's layout to optimize the arrangement of functional blocks in the final circuit. This optimization enhances the overall performance and efficiency of the final integrated circuit.
6. The method of claim 1 further comprising: receiving a plurality of physical design parameters for a final physical design implementation for said integrated circuit; and taking into account said physical design parameters in said creating so that said physical design implementation correlates with said final physical design implementation to a greater extent.
The integrated circuit design method of Claim 1 also includes receiving a set of physical design parameters for the final integrated circuit's physical implementation. These parameters are considered during the initial creation of the physical design implementation. This consideration ensures that the preliminary physical design implementation closely correlates with the final physical design implementation. This correlation helps reduce discrepancies and improve the accuracy of the design process.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
September 10, 2012
September 17, 2013
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