A semiconductor integrated circuit includes: a delay locked loop (DLL) configured to generate a DLL clock signal by delaying a source clock signal by a first delay time for obtaining a lock, wherein an update period of the DLL is controlled in response to an update period control signal after locking is completed; and an update period controller configured to generate the update period control signal based on a second delay time occurring in a loop path of the DLL in response to the source clock signal and a plurality of control signals provided from the DLL.
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1. A semiconductor integrated circuit comprising: a delay locked loop (DLL) configured to generate a DLL clock signal by delaying a source clock signal by a first delay time for obtaining a lock, wherein an update period of the DLL is controlled in response to an update period control signal after locking is completed; and an update period controller configured to generate the update period control signal based on a second delay time occurring in a loop path of the DLL in response to the source clock signal and a plurality of control signals provided from the DLL.
The semiconductor integrated circuit includes a Delay Locked Loop (DLL) that creates a DLL clock signal by delaying an input clock signal (source clock) until it's locked. After locking, the DLL's update speed is controlled by an "update period control signal." An "update period controller" generates this control signal. It calculates the correct update speed based on how long it takes signals to travel through the DLL's internal loop, the source clock, and other control signals from the DLL.
2. The semiconductor integrated circuit of claim 1 , wherein the DLL comprises: a first delay line configured to delay the source clock signal by the first delay line in response to a delay control signal and output the DLL clock signal; a first replica delay configured to delay the DLL clock signal by a third delay time equal to a delay through a clock path and output a feedback clock signal; a first signal generation unit configured to generate a clock phase comparison signal and a locking completion signal in response to the source clock signal and the feedback clock signal; and a second signal generation unit configured to generate the delay control signal in response to the clock phase comparison signal and the update period control signal.
The DLL in this circuit uses a delay line to delay the source clock signal based on a delay control signal to create the DLL clock signal. A "replica delay" mimics the delay caused by clock paths and outputs a feedback clock signal. A signal generator compares the source clock and feedback clock to generate a "clock phase comparison signal" and a "locking completion signal." Another signal generator uses the clock phase comparison signal and the update period control signal (from Claim 1) to create the delay control signal.
3. The semiconductor integrated circuit of claim 2 , wherein the plurality of control signals comprise the delay control signal and the locking completion signal.
The plurality of control signals used by the update period controller to control the update period of the DLL (mentioned in Claim 1) includes the delay control signal which controls the delay line in the DLL (from Claim 2) and the locking completion signal (from Claim 2) that indicates when the DLL has achieved a stable lock.
4. The semiconductor integrated circuit of claim 2 , wherein the second delay time comprises the first delay time and the third delay time.
The "second delay time occurring in a loop path of the DLL" (mentioned in Claim 1), which is used by the update period controller to determine how frequently to update the DLL, is composed of the initial delay applied to the source clock signal by the first delay line (from Claim 2), plus the delay introduced by the replica delay in the feedback path, which simulates the clock path delay (from Claim 2).
5. The semiconductor integrated circuit of claim 2 , wherein the first signal generation unit comprises: a phase comparison section configured to compare phases of the source clock signal and the feedback clock signal and output the clock phase comparison signal based on the phrase comparison; and an edge detection section configured to output the locking completion signal in response to the clock phase comparison signal.
The first signal generation unit described in Claim 2 includes a phase comparison section that compares the timing of the source clock signal and the feedback clock signal and generates the clock phase comparison signal reflecting any difference. It also includes an edge detection section that monitors the clock phase comparison signal and outputs the locking completion signal when the phase difference is small enough, indicating the DLL is locked.
6. The semiconductor integrated circuit of claim 2 , wherein the second signal generation unit comprises a filter configured to filter the clock phase comparison signal.
The second signal generation unit (from Claim 2) responsible for generating the delay control signal for the DLL uses a filter to smooth out the clock phase comparison signal before generating the delay control signal. This filtering reduces jitter and noise, improving the stability of the DLL.
7. The semiconductor integrated circuit of claim 4 , wherein the update period controller comprises: a third signal generation unit configured to generate a synchronized locking completion signal and the update period control signal in response to the source clock signal, the locking completion signal, and a delayed locking completion signal; and a fourth signal generation unit configured to delay the synchronized locking completion signal by the second delay time or a part of the second delay time and generate the delayed locking completion signal.
The update period controller (from Claim 1) includes a third signal generation unit that takes the source clock, locking completion signal, and a delayed version of the locking completion signal to create a synchronized locking completion signal and the update period control signal. A fourth signal generation unit delays the synchronized locking completion signal by a time equal to the "second delay time" (first delay time + third delay time, from Claim 4) or a portion of it, creating the "delayed locking completion signal."
8. The semiconductor integrated circuit of claim 7 , wherein the fourth signal generation unit comprises: a second delay line configured to delay the synchronized locking completion signal by the first delay time; and a second replica delay configured to delay an output signal of the second delay line by the third delay time and output the delayed locking completion signal.
The fourth signal generation unit (from Claim 7), which creates the delayed locking completion signal, uses a second delay line to delay the synchronized locking completion signal by the "first delay time" (the initial DLL delay). It then uses a second replica delay that mimics the clock path delay ("third delay time") to further delay the signal, outputting the final "delayed locking completion signal."
9. The semiconductor integrated circuit of claim 7 , wherein the third signal generation unit comprises: a synchronization section configured to synchronize the locking completion signal with the source clock signal and output the synchronized locking completion signal; an enable signal generation section configured to generate an enable signal in response to the synchronized locking completion signal and the delayed locking completion signal; and an output section configured to output the update period control signal in response to the enable signal and the source clock signal.
The third signal generation unit (from Claim 7) responsible for creating the update period control signal is further broken down into a synchronization section that synchronizes the locking completion signal with the source clock signal and outputs a synchronized version. An enable signal generation section creates an enable signal based on the synchronized and delayed locking completion signals. An output section generates the final update period control signal based on this enable signal and the source clock signal.
10. The semiconductor integrated circuit of claim 9 , wherein the synchronization section and the enable signal generation section comprise a D flip-flop.
The synchronization section and the enable signal generation section (from Claim 9) are implemented using a D flip-flop. The flip-flop synchronizes the locking completion signal to the source clock and generates an enable signal that is active when the synchronized locking completion signal is active and the delayed locking completion signal is inactive.
11. The semiconductor integrated circuit of claim 9 , wherein the output section comprises: an output limiter configured to output the source clock signal during a period that the enable signal is activated; and a counter configured to count the source clock signal outputted from the output limiter.
The output section (from Claim 9) includes an output limiter, such as an AND gate, that only allows the source clock signal to pass through when the enable signal is active. A counter counts the number of source clock pulses that pass through the output limiter. This count determines the update period of the DLL.
12. The semiconductor integrated circuit of claim 11 , wherein the output section further comprises an adder configured to add a first value to a counted value outputted from a counter and output the update period control signal.
The output section (from Claim 11) further includes an adder that adds a fixed value to the count produced by the counter before outputting the update period control signal. This allows for fine-tuning the update period and compensating for any offsets or systematic errors.
13. The semiconductor integrated circuit of claim 11 , wherein the output limiter comprises an AND gate configured to perform an AND operation on the enable signal and the source clock signal.
The output limiter (from Claim 11) which controls the passage of the source clock signal to the counter, is specifically implemented as an AND gate. The AND gate performs a logical AND operation on the enable signal (that determines when the DLL has locked) and the source clock signal, only allowing the clock signal to pass when both inputs are high.
14. The semiconductor integrated circuit of claim 2 , further comprising: an input buffer configured to buffer an external clock signal and generate the source clock signal; and an output driver configured to output data in synchronization with the DLL clock signal.
The semiconductor integrated circuit (from Claim 2) also includes an input buffer that receives an external clock signal and converts it into the "source clock signal" used by the DLL. An output driver is used to output data, ensuring the data is synchronized with the DLL clock signal, improving timing accuracy.
15. The semiconductor integrated circuit of claim 14 , wherein the third delay time comprises a delay time equal to a delay through a clock input path including the input buffer and a delay time equal to a delay through a clock output path including the output driver.
The "third delay time" (clock path delay mentioned in Claim 2) consists of two parts: the delay introduced by the clock input path, which includes the input buffer (from Claim 14), and the delay introduced by the clock output path, including the output driver (from Claim 14). This ensures the replica delay accurately mimics the total clock path delay.
16. A method for driving a semiconductor integrated circuit which includes a DLL configured to generate a DLL clock signal by delaying a source clock by a first delay time for obtaining a lock and an update period controller configured to control an update period of the DLL, the method comprising: generating, by the DLL, the DLL clock signal by delaying a source clock signal by the first delay time, wherein the first delay time is variably controlled; controlling, by the update period controller, the update period based on a second delay time that occurs in a loop path of the DLL in a state in which the generating of the DLL dock signal is completed; and performing, by the DLL, an update in response to the controlled update period.
A method for driving the semiconductor integrated circuit involves the DLL generating a DLL clock signal by delaying the source clock signal by a variable first delay time until locked. The update period controller then adjusts the DLL's update speed based on the "second delay time" (the time it takes for signals to travel through the DLL loop). Once this update period is controlled, the DLL performs updates at the set frequency.
17. The method of claim 16 , wherein the second delay time comprises the first delay time and a third delay time equal to a delay through a clock path.
The method (from Claim 16) specifies that the "second delay time," used to calculate the update period, includes the "first delay time" (the initial delay applied by the DLL) and a "third delay time" which is equal to the expected delay through a representative clock path within the semiconductor integrated circuit.
18. The method of claim 16 , wherein the controlling of the update period comprises: activating, by the DLL, a locking completion signal as the generating of the DLL clock signal is completed; counting, by the update period controller, the source clock signal during the second delay time and outputting the counted value, as the locking completion signal is activated; and performing, by the DLL, an update in response to the update period controlled according to the counted value.
The method for driving the semiconductor integrated circuit (from Claim 16) involves the DLL activating a locking completion signal when the DLL clock signal generation is completed and locked. The update period controller counts the source clock signal during the "second delay time" (time through the DLL loop) after the locking completion signal is activated. The DLL then updates its state based on the counted value, effectively controlling its update frequency.
19. The method of claim 18 , wherein the outputting of the counted value comprises: synchronizing the locking completion signal with the source clock signal and generating the synchronized locking completion signal; generating a delayed locking completion signal by delaying the synchronized locking completion signal by the second delay time and generating an enable signal having an activation period in response to the synchronized locking completion signal and the delayed locking completion signal; and counting the toggling number of the source clock signal during the activation period of the enable signal.
In the method (from Claim 18), the counted value used to determine the DLL update frequency is generated by synchronizing the locking completion signal with the source clock, creating a synchronized locking completion signal. A delayed locking completion signal is created by delaying the synchronized signal by the "second delay time." An enable signal with an activation period is generated in response to both the synchronized and delayed locking completion signals. Finally, the number of toggles (rising or falling edges) of the source clock signal are counted only during the activation period of the enable signal.
20. The method of claim 18 , wherein the outputting of the counted value comprises: adding a first value to the counted value.
In the method (from Claim 18), after counting the source clock signal over the "second delay time," a fixed value is added to the counted value. The DLL's update period is then based on this adjusted value, allowing for fine-tuning or calibration of the DLL update frequency.
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December 22, 2011
September 24, 2013
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