An embedded controller includes a microcontroller core, a first bus interface that does not support bus arbitration, a second bus interface and memory control circuitry. The first bus interface is configured to receive and transmit memory transactions from and to a Central Processing Unit (CPU) chipset. The second bus interface is configured to communicate with a memory and to transfer the memory transactions of the CPU chipset to and from the memory. The memory control circuitry is configured to evaluate a starvation condition that identifies an inability of the microcontroller core to access the memory via the second bus interface due to the memory transactions transferred between the CPU chipset and the memory via the first and second bus interfaces, and to invoke a predefined corrective action when the starvation condition is met.
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1. An embedded controller, comprising: a microcontroller core; a first bus interface, which is configured to receive and transmit memory transactions from and to a Central Processing Unit (CPU) chipset and does not support bus arbitration; a second bus interface, which is configured to communicate with a memory and to transfer the memory transactions of the CPU chipset to and from the memory; and memory control circuitry, which is configured to evaluate a starvation condition that identifies an inability of the microcontroller core to access the memory via the second bus interface due to the memory transactions transferred between the CPU chipset and the memory via the first and second bus interfaces, and to invoke a predefined corrective action when the starvation condition is met.
An embedded controller mitigates starvation when sharing SPI flash. It has a microcontroller core and two bus interfaces. The first interface receives memory requests from a CPU chipset but lacks bus arbitration. The second interface communicates with shared memory, transferring CPU chipset requests to the memory. Memory control circuitry monitors whether the microcontroller core is unable to access the memory due to CPU chipset activity. If this "starvation condition" occurs, the circuitry takes a predefined corrective action to resolve the memory access conflict.
2. The embedded controller according to claim 1 , wherein the memory control circuitry is configured to evaluate the starvation condition by detecting that no successful fetch transactions occur between the microcontroller core and the memory within a predetermined time period.
The embedded controller from the previous description determines the "starvation condition" by checking if the microcontroller core successfully fetches data from memory within a set time period. If no successful fetches occur during that period, it considers the core to be starved of memory access and initiates a corrective action. This detects when CPU chipset operations prevent the microcontroller core from accessing necessary data in a timely manner.
3. The embedded controller according to claim 1 , wherein the memory control circuitry is configured to evaluate the starvation condition by detecting that a number of successful fetch transactions, initiated by the EC microcontroller core via the second bus interface to the memory, is below a predetermined threshold.
The embedded controller from the initial description determines the "starvation condition" by counting the number of successful data fetch operations that the microcontroller core initiates to the memory. If the number of fetches falls below a pre-determined threshold, the controller recognizes the starvation condition and takes corrective action to address the memory access issues, ensuring the microcontroller is not blocked by CPU chipset activity.
4. The embedded controller according to claim 1 , wherein the memory control circuitry is configured to evaluate the starvation condition by detecting that the microcontroller core fails to access the memory within a predetermined time period.
The embedded controller from the initial description identifies a "starvation condition" by determining whether the microcontroller core can access the memory within a defined time period. If the microcontroller core consistently fails to access memory within this window, the controller detects the starvation and invokes a predefined corrective action. This method ensures the microcontroller core is not indefinitely blocked from accessing memory due to competing CPU chipset operations.
5. The embedded controller according to claim 1 , wherein the memory control circuitry is configured to evaluate the starvation condition by estimating an average length of fetch transactions between the microcontroller core and the memory.
The embedded controller from the initial description determines the "starvation condition" by estimating the average duration of data fetch transactions between the microcontroller core and the memory. By monitoring the average fetch time, the controller detects increases that indicate potential memory access conflicts or delays, and can invoke corrective action when this average exceeds a specified threshold, preventing excessive memory access latency.
6. The embedded controller according to claim 1 , and comprising a watchdog circuit that is configured to monitor an expected progress of software executed by the microcontroller core, wherein the memory control circuitry is configured to evaluate the starvation condition by detecting a deviation from the expected progress using the watchdog circuit.
The embedded controller from the initial description includes a watchdog circuit. This circuit monitors the expected progress of the software running on the microcontroller core. The memory control circuitry uses the watchdog to determine the "starvation condition" by detecting deviations from the expected software progress. If the watchdog detects a significant deviation, it indicates a memory access issue preventing software execution, and a corrective action is triggered.
7. The embedded controller according to claim 1 , wherein the microcontroller core comprises a cache memory for caching memory access operations between the microcontroller core and the memory, and wherein the memory control circuitry is configured to evaluate the starvation condition based only on the memory access operations that are not served from the cache memory.
The embedded controller from the initial description includes a cache memory in the microcontroller core. This cache stores recent memory access operations. The memory control circuitry only evaluates the "starvation condition" based on memory access operations that are *not* served by the cache. This focuses starvation detection on actual memory access bottlenecks, ignoring accesses handled by the cache, thus avoiding false positives due to cache hits masking underlying memory access problems.
8. The embedded controller according to claim 1 , wherein the memory control circuitry is configured to assign to the inability of the microcontroller core to access the memory a starvation severity level, selected from a set of multiple different severity levels, and to invoke the predefined corrective action depending on the assigned starvation severity level.
The embedded controller from the initial description assigns a "starvation severity level" to the inability of the microcontroller core to access memory. This level is selected from a set of severity levels. The specific corrective action invoked depends on the assigned starvation severity level. For example, a low severity might only trigger a retry, while a high severity might trigger a system shutdown.
9. The embedded controller according to claim 1 , wherein the memory control circuitry is configured to invoke the corrective action by initiating a shut-down of a computer comprising the embedded controller and the CPU chipset.
The embedded controller from the initial description invokes a corrective action by initiating a shutdown of the computer containing the embedded controller and the CPU chipset. This is done when a "starvation condition" is detected where the microcontroller core cannot access memory. Shutting down the entire system prevents further data corruption or system instability caused by prolonged memory access failures.
10. The embedded controller according to claim 9 , wherein the memory control circuitry is configured to initiate the shut-down of the computer without prior notification to the CPU chipset.
The embedded controller from the previous description initiates a computer shutdown without first notifying the CPU chipset. This corrective action, triggered by a "starvation condition," is performed autonomously by the embedded controller, ensuring a rapid response to prevent further system damage or data corruption without relying on the CPU chipset to respond or cooperate.
11. The embedded controller according to claim 9 , wherein the memory control circuitry is configured to request software running on a CPU of the computer to shut-down the computer.
The embedded controller from the description of shutting down a computer invokes a corrective action by requesting software running on the CPU of the computer to initiate the shutdown. Instead of directly halting the system, the embedded controller signals the CPU to perform a controlled shutdown, allowing the CPU to gracefully close applications and save data before the system powers down, preventing data loss.
12. The embedded controller according to claim 1 , wherein the microcontroller core is configured to invoke the corrective action by switching to run the embedded controller using emergency software code that is not fetched in real time from the memory over the second bus interface.
The embedded controller from the initial description addresses memory starvation by switching to run using emergency software code. This code is not fetched in real time from the shared memory. Instead, it's likely stored internally within the controller. This allows the controller to continue operating in a limited capacity even when memory access is blocked, maintaining critical functions.
13. The embedded controller according to claim 12 , and comprising an additional microcontroller core that is configured to execute the emergency software code in response to detection of the starvation condition.
The embedded controller from the previous description of running using emergency software includes an additional microcontroller core. This extra core is specifically configured to execute the emergency software code when the "starvation condition" is detected. The primary microcontroller hands off control to this secondary core, allowing the system to continue functioning with the emergency software without relying on the potentially blocked primary core.
14. A method, comprising: in an embedded controller, receiving and transmitting memory transactions from and to a Central Processing Unit (CPU) chipset over a first bus interface that does not support bus arbitration, and communicating with a memory and transferring the memory transactions of the CPU chipset to and from the memory over a second bus interface; evaluating a starvation condition that identifies an inability of the embedded controller to access the memory via the second bus interface due to the memory transactions transferred between the CPU chipset and the memory via the first and second bus interfaces; and invoking a predefined corrective action when the starvation condition is met.
A method for mitigating embedded controller starvation involves receiving memory transactions from a CPU chipset over a first bus without arbitration, and communicating with shared memory over a second bus. The method evaluates a "starvation condition" where the embedded controller can't access memory because of CPU chipset transactions. If the condition is met, a predefined corrective action is taken to ensure the embedded controller can still operate correctly.
15. The method according to claim 14 , wherein evaluating the starvation condition comprises detecting that no successful fetch transactions occur between the embedded controller and the memory within a predetermined time period.
The method of mitigating embedded controller starvation, as previously described, evaluates the "starvation condition" by checking for successful memory fetch transactions within a set period. If no successful fetches occur, it indicates starvation. This detects if the embedded controller is blocked from accessing the shared memory and requires a corrective action to resolve the memory access conflict.
16. The method according to claim 14 , wherein evaluating the starvation condition comprises detecting that a number of successful fetch transactions, initiated by the embedded controller to the memory over the second bus interface, is below a predetermined threshold.
The method of mitigating embedded controller starvation, as previously described, evaluates the "starvation condition" by counting the number of successful data fetch operations by the embedded controller to the shared memory. If this number falls below a threshold, it indicates a potential memory starvation, causing corrective action to be taken, which ensures the embedded controller isn't prevented from accessing required data.
17. The method according to claim 14 , wherein evaluating the starvation condition comprises detecting that the embedded controller fails to access the memory within a predetermined time period.
The method of mitigating embedded controller starvation, as previously described, involves detecting a "starvation condition" by monitoring if the embedded controller fails to access the shared memory within a defined time period. Failure to access the memory within the allotted time suggests the embedded controller is blocked from accessing memory and requires a defined corrective action to avoid issues.
18. The method according to claim 14 , wherein evaluating the starvation condition comprises estimating an average length of fetch transactions between the embedded controller and the memory.
The method of mitigating embedded controller starvation, as previously described, evaluates the "starvation condition" by calculating an average length of fetch transactions between the embedded controller and the memory. A longer average length suggests access issues. This helps to recognize memory access delays, allowing for a corrective action when the average length exceeds a set value, which avoids issues with delays caused by memory conflicts.
19. The method according to claim 14 , wherein evaluating the starvation condition comprises detecting a deviation from an expected progress of software executed by the embedded controller, using a watchdog circuit that monitors the expected progress of the software.
The method of mitigating embedded controller starvation, as previously described, uses a watchdog circuit to monitor expected software progress. The "starvation condition" is determined by detecting deviations from this expected progress. If the watchdog identifies a significant deviation, it signals a likely memory access problem preventing software advancement and initiates a defined corrective action to resolve issues with memory.
20. The method according to claim 14 , wherein the embedded controller comprises a cache memory for caching memory access operations between the embedded controller and the memory, and wherein evaluating the starvation condition comprises assessing the starvation condition based only on the memory access operations that are not served from the cache memory.
The method of mitigating embedded controller starvation, as previously described, considers cache memory. The "starvation condition" is assessed only on memory accesses *not* served by the cache. This focuses the starvation detection on actual memory bottlenecks, preventing misleading alerts from cache hits that conceal underlying memory access issues, thereby ensuring appropriate corrective action is used.
21. The method according to claim 14 , wherein evaluating the starvation condition comprises assigning to the inability of the embedded controller to access the memory a starvation severity level, selected from a set of multiple different severity levels, and wherein invoking the predefined corrective action comprises selecting the corrective action depending on the assigned starvation severity level.
The method of mitigating embedded controller starvation, as previously described, assigns a "starvation severity level" to the controller's inability to access memory, chosen from a range of levels. The corrective action depends on the assigned severity. A lower severity might trigger a simple retry, while a more severe level could result in a system shutdown.
22. The method according to claim 14 , wherein invoking the corrective action comprises initiating a shut-down of a computer that comprises the embedded controller and the CPU chipset.
The method of mitigating embedded controller starvation, as previously described, involves initiating a system shutdown as a corrective action. This is triggered when the embedded controller is starved of memory access and involves shutting down the computer that includes the embedded controller and CPU chipset.
23. The method according to claim 22 , wherein initiating the shut-down comprises shutting-down the computer without prior notification to the CPU chipset.
The method of shutting down a computer as a corrective action, as described in the previous memory mitigation method, does so without notifying the CPU chipset. This autonomous shutdown protects against data corruption or system damage by directly halting the system and ensuring memory access problems don't cause further instability or damage to the system or software.
24. The method according to claim 22 , wherein initiating the shut-down comprises requesting software running on a CPU of the computer to shut-down the computer.
The method of shutting down a computer as a corrective action, as described in the memory starvation mitigation method, involves requesting the system's CPU to perform the shutdown. The embedded controller signals the CPU to shutdown, providing a controlled system shutdown and graceful termination of programs, thereby preventing data loss before powering down.
25. The method according to claim 14 , wherein invoking the corrective action comprises switching to run the embedded controller using emergency software code that is not fetched in real time from the memory over the second bus interface.
The method of mitigating embedded controller starvation, as previously described, invokes a corrective action by switching the embedded controller to run emergency software code. This software is not fetched from memory in real time, allowing for the continued, even if limited, operation of the embedded controller, even with the original shared memory blocked or unavailable.
26. The method according to claim 25 , wherein the embedded controller comprises a microcontroller core that runs software code when the starvation condition is not met, and wherein invoking the corrective action comprises causing an additional microcontroller core in the embedded controller to execute the emergency software code upon meeting the starvation condition.
The method of mitigating embedded controller starvation, as previously described, contains a microcontroller core that runs code when starvation is absent. If the "starvation condition" occurs, a second microcontroller core executes emergency software, avoiding memory access dependency by running previously stored emergency code. This switches processes, allowing a secondary core to run in emergency conditions.
27. A computer, comprising: a Central Processing Unit (CPU) chipset; a memory; and an embedded controller, comprising: a microcontroller core; a first bus interface, which is configured to receive and transmit memory transactions from and to the CPU chipset and does not support bus arbitration; a second bus interface, which is configured to communicate with the memory and to transfer the memory transactions of the CPU chipset to and from the memory; and memory control circuitry, which is configured to evaluate a starvation condition that identifies an inability of the microcontroller core to access the memory via the second bus interface due to the memory transactions transferred between the CPU chipset and the memory via the first and second bus interfaces, and to invoke a predefined corrective action when the starvation condition is met.
A computer system contains a CPU chipset, memory, and an embedded controller to resolve memory starvation. The embedded controller includes a microcontroller core, a first bus interface that receives memory requests from the CPU chipset without arbitration, and a second bus interface to access the shared memory. Memory control circuitry checks for a "starvation condition" caused by CPU chipset activity that prevents the microcontroller core from accessing the memory. If this is identified, a predefined corrective action is activated to resolve memory conflicts.
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January 29, 2012
September 24, 2013
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