Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming of such memory devices includes determining a rate of programming (i.e., rate of movement of the respective threshold voltage) of the memory cells and biasing the corresponding bit line with a programming rate control voltage that is greater than the bit line enable voltage and less than the inhibit voltage. This voltage can be adjusted to change the speed of programming. A capacitor coupled to the bit line stores the programming rate control voltage in order to maintain the proper bit line bias for the duration of the programming operation or until it is desired to change the programming rate.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A device comprising: an array of memory cells; and a controller circuit coupled to the array of memory cells, the controller circuit configured to identify a memory cell of the array of memory cells having a faster programming rate than another memory cell and program the memory cell having the faster programming rate different than the other memory cell.
2. The device of claim 1 wherein the controller circuit is further configured to store an indication of a location of the memory cell having the faster programming rate.
3. The device of claim 2 wherein the controller circuit is further configured to store the indication in a table assigned to a block of memory that includes the memory cell having the faster programming rate.
4. The device of claim 1 wherein the controller circuit is further configured to store an indication of the programming rate of the memory cell having the faster programming rate.
5. The device of claim 4 wherein the indication of the programming rate represents an amount of change of a threshold voltage of the memory cell in response to a rate identification biasing.
6. The device of claim 1 wherein the memory cell having the faster programming rate is coupled to a bit line and the controller circuit is further configured to write a bit line bias to a capacitor coupled to the bit line.
7. The device of claim 6 wherein the controller circuit is further configured to write the selected bit line bias to the capacitor during a programming operation.
8. A system comprising: a memory device comprising an array of memory cells; and a controller circuit coupled to the array of memory cells, the controller circuit configured to identify a memory cell of the array of memory cells having a faster programming rate than another memory cell of the array of memory cells and use a redundant memory cell in place of the memory cell having the faster programming rate.
9. The system of claim 8 wherein the controller circuit is further configured to mark the memory cell having the faster programming rate as being defective.
10. The system of claim 8 wherein the controller circuit is further configured to use a redundant memory cell from a redundant memory column in place of the memory cell having the faster programming rate.
11. The system of claim 8 and further comprising: a plurality of bit lines, each bit line coupled to a column of memory cells of the array of memory cells; and a plurality of bias capacitors, each capacitor coupled to a different bit line, wherein the controller circuit is further configured to write a voltage to the capacitor coupled to the bit line that is coupled to the memory call having the faster programming rate such that the controller circuit is configured to adjust the voltage responsive to the programming rate.
12. The system of claim 11 wherein the controller circuit is further configured to dynamically determine how to bias the bit line coupled to the memory cell having the faster programming rate.
13. The system of claim 11 wherein the controller circuit is configured to write different voltages to capacitors coupled to other bit lines responsive to a programming rate of each memory cell coupled to the respective bit lines.
14. A system comprising: a memory device comprising an array of memory cells; and a controller circuit coupled to the memory device and configured to receive a program/write command that contains an address of a memory cell and a data value to program, determine whether the memory cell is a faster programming memory cell than other memory cells of the array of memory cells responsive to the address, read data describing a bit line bias associated with the address when the memory cell is determined to be a faster programming memory cell, and use the data to generate the bit line bias for a bit line coupled to the memory cell.
15. The system of claim 14 wherein the controller circuit is further configured to apply the bit line bias for the bit line coupled to the memory cell to a capacitor coupled to the bit line.
16. The system of claim 14 wherein the controller circuit is further configured to slow a programming rate of the memory cell if it is farther ahead in programming with respect to other memory cells coupled to a word line that is coupled to the memory cell.
17. The system of claim 16 wherein the controller circuit is further configured to slow the programming by adjusting a bias of a bit line coupled to the memory cell so that the memory cell and the other memory cells reach their respective programmed states substantially simultaneously.
18. The system of claim 16 wherein the controller circuit being configured to determine whether a memory cell is farther ahead in programming in relation to other memory cells takes into account a percentage of completion of programming of the memory cell.
19. The system of claim 16 wherein the controller circuit being configured to determine whether a memory cell is farther ahead in programming in relation to other memory cells comprises determining whether the memory cell has a threshold voltage that is closer to being in its programmed state than the other memory cells.
20. The system of claim 14 wherein the controller circuit is configured to store an indication of a programming rate of the faster programming memory cell.
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April 24, 2012
October 1, 2013
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