According to example embodiments of inventive concepts, a method of fabricating a semiconductor device includes forming a sacrificial pattern having SiGe on a crystalline silicon substrate. A body having crystalline silicon is formed on the sacrificial pattern. At least one active element is formed on the body. An insulating layer is formed to cover the sacrificial pattern, the body, and the active element. A contact hole is formed to expose the sacrificial pattern through the insulating layer. A void space is formed by removing the sacrificial pattern. An amorphous silicon layer is formed in the contact hole and the void space. The amorphous silicon layer is transformed into a metal silicide layer.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of fabricating a semiconductor device, comprising: forming a sacrificial pattern having SiGe on a substrate, the substrate having crystalline silicon; forming a body on the sacrificial pattern, the body having crystalline silicon; forming at least one active element on the body; forming an insulating layer that covers the sacrificial pattern, the body and the at least one active element; forming a contact hole to expose the sacrificial pattern through the insulating layer; forming a void space by removing the sacrificial pattern; forming an amorphous silicon layer in the contact hole and the void space; and transforming the amorphous silicon layer into a metal silicide layer.
2. The method according to claim 1 , wherein the forming the sacrificial pattern includes performing a first epitaxial growth process, and the forming the body includes performing a second epitaxial growth process.
3. The method according to claim 1 , wherein the sacrificial pattern directly contacts the substrate and the body.
4. The method according to claim 1 , wherein the substrate and the body include P-type impurities.
5. The method according to claim 1 , wherein the amorphous silicon layer directly contacts the substrate and the body, and the metal silicide layer directly contacts the substrate and the body.
6. The method according to claim 1 , further comprising: forming a core that is surrounded by the metal silicide layer.
7. The method according to claim 6 , wherein the core is formed in the contact hole, and the metal silicide layer fills the void space and surrounds side surfaces of the core.
8. The method according to claim 6 , wherein the core is formed in the void space and the contact hole, and the metal silicide layer surrounds a surface of the core.
9. The method according to claim 1 , further comprising: forming a conductive plug in the contact hole and on the metal silicide layer, wherein the conductive plug contacts the metal silicide layer.
10. The method according to claim 1 , wherein the transforming the amorphous silicon layer into the metal silicide layer includes: forming a metal layer that contacts the amorphous silicon layer, and heat-treating the metal layer and the amorphous silicon layer.
11. The method according to claim 10 , wherein the forming the at least one active element includes: forming a gate dielectric layer on the body before the forming the metal layer, and forming a gate electrode on the gate dielectric layer.
12. A method of fabricating a semiconductor device, comprising: forming a sacrificial pattern on a substrate; forming an active element on the sacrificial pattern; forming an insulating layer that covers the sacrificial pattern and the active element; forming a contact hole to expose the sacrificial pattern through the insulating layer; forming a void space by removing the sacrificial pattern; forming an amorphous silicon layer in the contact hole and the void space; transforming the amorphous silicon layer into a metal silicide layer; and forming a conductive pattern on the metal silicide layer.
13. The method according to claim 12 , wherein the forming the metal silicide layer and the forming the conductive pattern includes; exposing an upper end region of the contact hole by etching-back the amorphous silicon layer; forming a metal layer in the upper end region of the contact hole; forming the metal silicide layer by heat-treating the metal layer and the amorphous silicon layer; exposing the upper end region of the contact hole by removing the metal layer; and forming the conductive pattern in the upper end region of the contact hole.
14. The method according to claim 12 , wherein forming the metal silicide layer and the conductive pattern includes; forming the amorphous silicon layer to cover side walls of the contact hole and fill the void space; forming a metal layer on the amorphous silicon layer; forming the metal silicide layer by heat-treating the metal layer and the amorphous silicon layer; removing the metal layer; and forming the conductive pattern on the metal silicide layer, wherein the conductive pattern is formed in the contact hole, the metal silicide layer is formed to fill the void space, and the metal silicide layer is formed to surround side surfaces of the conductive pattern.
15. The method according to claim 12 , wherein forming the metal silicide layer and the conductive pattern includes; forming the amorphous silicon layer on side walls of the contact hole and inner walls of the void space; forming a metal layer on the amorphous silicon layer; forming the metal silicide layer by heat-treating the metal layer and the amorphous silicon layer; removing the metal layer; and forming the conductive pattern on the metal silicide layer, wherein the conductive pattern is formed in the contact hole and the void space, and the metal silicide layer is formed to surround the conductive pattern.
16. A method of fabricating a semiconductor device, comprising: forming a sacrificial pattern on a substrate; forming a stacked structure including at least one active element on the sacrificial pattern, the stacked structure defining at least one contact hole that exposes the sacrificial pattern; removing the sacrificial pattern to form a void pattern between the substrate and the stacked structure; forming an amorphous silicon layer in the at least one contact hole and the void pattern, the amorphous silicon layer partially filling at least one of the at least one contact hole and the void pattern; transforming the amorphous silicon layer into a metal silicide layer; forming a conductive pattern on the metal silicide layer; and forming a conductive plug in at least one of the at least one contact hole and the void pattern after the transforming the amorphous silicon layer into the metal silicide layer.
17. The method of claim 16 , wherein a part of the metal silicide layer surrounds a part of the conductive plug.
18. The method claim 16 , wherein a lowermost surface of the conductive plug is on an uppermost surface of the metal silicide layer.
19. The method of claim 16 , wherein the transforming the amorphous silicon layer into the metal silicide layer includes: forming a metal layer that contacts the amorphous silicon layer, and heat-treating the metal layer and the amorphous silicon layer.
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July 17, 2012
October 15, 2013
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