A nonvolatile semiconductor memory apparatus including a substrate, lower-layer electrode wires provided on the substrate, an interlayer insulating layer provided with contact holes at locations respectively opposite to the lower-layer electrode wires, resistance variable layers which are respectively connected to the lower-layer electrode wires; and non-ohmic devices which are respectively provided on the resistance variable layers. The non-ohmic devices each has a laminated-layer structure including plural semiconductor layers, a laminated-layer structure including a metal electrode layer and an insulator layer, or a laminated-layer structure including a metal electrode layer and a semiconductor layer. One layer of the laminated-layer structure is embedded to fill each of the contact holes and the semiconductor layer or the insulator layer which is the other layer of the laminated-layer structure has a larger area than an opening of each of the contact holes and is provided on the interlayer insulating layer.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of manufacturing a nonvolatile semiconductor memory apparatus comprising: a step for forming stripe-shaped lower-layer electrode wires on a substrate; a step for forming an interlayer insulating layer on the substrate including the lower-layer electrode wires; a step for forming contact holes in an interlayer insulating layer at locations respectively opposite to the lower-layer electrode wires; a step for embedding resistance variable layers to fill the contact holes except for portions at an upper side of the interlayer insulating layer; a step for embedding at least one layers of laminated-layer structures respectively forming non-ohmic devices to fill the portions at the upper side of the contact holes; and a step for forming, on the interlayer insulating layer, the other layers of the laminated-layer structures respectively forming the non-ohmic devices such that the other layers have a larger area than openings of the contact holes.
2. The method of manufacturing the nonvolatile semiconductor memory apparatus according to claim 1 , wherein the step for embedding the resistance variable layers to fill the contact holes includes a step for forming, inside the contact holes and on the interlayer insulating layer, a first deposited film which is made of a material for the resistance variable layers and a step for removing a portion of the first deposited film which covers a surface of the interlayer insulating layer; and the step for embedding at least one layers of laminated-layer structures respectively forming non-ohmic devices to fill the portions at the upper side of the contact holes includes a step for removing portions of the first deposited film inside the contact holes to form recesses formed by the contact holes and the first deposited film, a step for forming, inside the recesses and on the interlayer insulating layer, a second deposited film which is made of a material for the at least one layers, and a step for removing a portion of the second deposited film which covers the surface of the interlayer insulating layer.
3. A method of manufacturing a nonvolatile semiconductor memory apparatus comprising the steps as recited in claim 1 plural times to stack the resistance variable layers and the non-ohmic devices to form a layer structure.
4. The method of manufacturing the nonvolatile semiconductor memory apparatus according to claim 1 , wherein the other layers of the laminated-layer structures respectively forming the non-ohmic devices are formed in stripe shape on the interlayer insulating layer so as to respectively cross the lower-layer electrode wires.
5. The method of manufacturing the nonvolatile semiconductor memory apparatus according to claim 1 , further comprising: forming stripe-shaped upper-layer electrode wires on the non-ohmic devices such that the upper-layer electrode wires are respectively connected to the non-ohmic devices and respectively cross the lower-layer electrode wires.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
July 31, 2012
October 15, 2013
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