Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor memory device, comprising: a) a stack position identifier for identifying a position of the semiconductor memory device in an aligned vertical stack of a plurality of semiconductor memory devices; b) a self-refresh oscillator configured to generate an oscillating signal to control a rate of self-refresh operations for the semiconductor memory device; and c) an oscillator adjustor configured to increase the self-refresh oscillator from a first frequency to a second frequency in response to the stack position identifier when the stack position identifier indicates that the semiconductor memory device is higher in the aligned vertical stack than at least one of the plurality of semiconductor memory devices.
2. The semiconductor memory device of claim 1 , further comprising a self-refresh counter configured to count a number of oscillations of the oscillating signal to determine when to initiate the self-refresh operations.
3. The semiconductor memory device of claim 1 , wherein the self-refresh oscillator comprises an odd-numbered plurality of inverting stages.
4. The semiconductor memory device of claim 3 , wherein at least one of the odd-numbered plurality of inverting stages comprises a pull-up transistor configured to charge a node that is coupled to another of the inverting stages.
5. The semiconductor memory device of claim 4 , further comprising an adjustment transistor coupled in parallel with the pull-up transistor, wherein the adjustment transistor is configured to be controllable by at least one bit of the stack position identifier.
6. The semiconductor memory device of claim 3 , wherein at least one of the odd-numbered plurality of inverting stages comprises a pull-down transistor configured to discharge a node that is coupled to another of the inverting stages.
7. The semiconductor memory device of claim 6 , further comprising an adjustment transistor coupled in parallel with the pull-down transistor, wherein the adjustment transistor is configured to be controllable by at least one bit of the stack position identifier.
8. The semiconductor memory device of claim 1 , wherein a through-silicon via (TSV) is configured to connect a signal to another semiconductor memory device in the aligned vertical stack of semiconductor memory devices.
9. The semiconductor memory device of claim 1 , wherein the second frequency is higher than the first frequency such that the self-refresh operations from the second frequency are configured to occur at an increased rate relative to the self-refresh operations from the first frequency.
10. A method of controlling a semiconductor memory device, the method comprising: a) identifying, by a stack position identifier, a position of the semiconductor memory device in an aligned vertical stack of a plurality of semiconductor memory devices; b) generating, by a self-refresh oscillator, an oscillating signal to control a rate of self-refresh operations for the semiconductor memory device; and c) adjusting the self-refresh oscillator from a first frequency to a second frequency in response to the stack position identifier when the stack position identifier indicates that the semiconductor memory device is higher in the aligned vertical stack than at least one of the plurality of semiconductor memory devices.
11. The method of claim 10 , further comprising initiating the self-refresh operations in response to a count of a number of oscillations of the oscillating signal.
12. The method of claim 10 , wherein the adjusting the self-refresh oscillator comprises changing a resistance in a path of a stage of the self-refresh oscillator.
13. The method of claim 12 , wherein the changing the resistance in the path comprises enabling an adjustment transistor that is coupled in parallel with at least one transistor in the path of the stage.
14. The method of claim 13 , wherein the enabling the adjustment transistor comprises using a gate control signal derived from at least one bit of the stack position identifier.
15. The method of claim 14 , wherein the self-refresh operations from the second frequency occur at an increased rate relative to the self-refresh operations from the first frequency.
16. An apparatus having an aligned vertical stack of a plurality of semiconductor memory devices, the apparatus comprising for each semiconductor memory device: a) a stack position identifier for identifying a position of the semiconductor memory device in the aligned vertical stack of the plurality of semiconductor memory devices; b) a self-refresh oscillator configured to generate an oscillating signal to control a rate of self-refresh operations for the semiconductor memory device; and c) an oscillator adjustor configured to increase the self-refresh oscillator from a first frequency to a second frequency in response to the stack position identifier when the stack position identifier indicates that the semiconductor memory device is higher in the aligned vertical stack than at least one of the plurality of semiconductor memory devices.
17. The apparatus of claim 16 , wherein the self-refresh oscillator comprises an odd-numbered plurality of inverting stages.
18. The apparatus of claim 17 , wherein at least one of the odd-numbered plurality of inverting stages comprises a path transistor configured to charge or discharge a node that is coupled to another of the inverting stages.
19. The apparatus of claim 18 , further comprising an adjustment transistor coupled in parallel with the path transistor, wherein the adjustment transistor is configured to be controllable by at least one bit of the stack position identifier.
20. The apparatus of claim 16 , wherein a through-silicon via (TSV) is configured to connect a signal between a first of the plurality of semiconductor memory devices and a second of the plurality of semiconductor memory devices in the aligned vertical stack.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
January 24, 2012
October 15, 2013
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