A semiconductor device includes a first wiring hoard, a second semiconductor chip, and a second seal. The first wiring board includes a first substrate, a first semiconductor chip, and a first seal. The first semiconductor chip is disposed on the first substrate. The first seal is disposed on the first substrate. The first seal surrounds the first semiconductor chip. The first seal has the same thickness as the first semiconductor chip. The second semiconductor chip is stacked over the first semiconductor chip. The first semiconductor chip is between the second semiconductor chip and the first substrate. The second semiconductor chip is greater in size in plan view than the first semiconductor chip. The second seal seals at least a first gap between the first semiconductor chip and the second semiconductor chip.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device comprising, a first semiconductor chip including a first surface, a second surface opposite to the first surface, a side surface joined to the first and second surfaces to define an edge thereof, and a first electrode formed on the second surface; a first seal that seals the side surface and includes a lower surface which is substantially coplanar with the second surface of the first semiconductor chip; a rewiring layer formed over the second surface of the first semiconductor chip and at least a part of the lower surface of the first seal, and electrically connected to the first electrode of the first semiconductor chip; a second semiconductor chip stacked over the first surface of the first semiconductor chip; and a second seal that seals at least a first gap between the first semiconductor chip and the second semiconductor chip, wherein the first semiconductor chip includes a second electrode formed on the first surface, the second electrode being electrically connected to the first electrode, and the second semiconductor chip includes a third electrode formed on a third surface thereof, the second semiconductor chip is stacked over the first surface of the first semiconductor chip so that the third electrode is electrically connected to the second electrode of the first semiconductor chip.
2. The semiconductor device according to claim 1 , wherein the second semiconductor chip includes a fourth electrode formed on a fourth surface that is opposite to the third surface, the fourth electrode being electrically connected to the third electrode.
3. The semiconductor device according to claim 1 , further comprising: a third semiconductor chip stacked over the second semiconductor chip, the second semiconductor chip being between the first semiconductor chip and the third semiconductor chip.
4. The semiconductor device according to claim 1 further comprising: an insulating layer formed in contact with the second surface of the first semiconductor chip and with the lower surface of the first seal so as to expose the first electrode of the first semiconductor chip.
5. The semiconductor device according to claim 3 , further comprising: a third seal that seals a second gap between the second and third semiconductor chips, and at least a side surface of the second semiconductor chip, wherein the second seal seals the first gap.
6. The semiconductor device according to claim 3 , further comprising: a supporting substrate adhered to the third semiconductor chip, the third semiconductor chip being between the second semiconductor chip and the supporting substrate.
7. The semiconductor device according to claim 2 , further comprising: a third seal that seals a side surface of the second semiconductor chip, the third seal includes an upper surface that is substantially coplanar with the fourth surface of the second semiconductor chip; and a second rewiring layer is formed over the fourth surface of the second semiconductor chip and at least a part of the upper surface of the third seal.
8. The semiconductor device according to claim 1 , wherein the first semiconductor chip is an interface chip or a logic chip, and the second semiconductor chip is a memory chip.
9. A device comprising: a first semiconductor chip including a first main surface and a second main surface opposite to the first main surface, the first semiconductor chip further including a plurality of chip electrodes on a side of the first main surface; a first seal including a third main surface and a fourth main surface opposite to the third main surface, the first seal including a hole formed therein and being substantially the same in thickness as the first semiconductor chip to accommodate the first semiconductor chip in the hole such that the third main surface of the first seal is substantially coplanar with the first main surface of the first semiconductor chip and the fourth main surface of the first seal is substantially coplanar with the second main surface of the first semiconductor chip; an insulating layer formed in contact with the first main surface of the first semiconductor chip and with the third main surface of the first seal, the insulating layer including a plurality of holes that expose the chip electrodes of the first semiconductor chip, respectively; a plurality of ball electrodes formed over the insulating layer apart from the chip electrodes; a plurality of rewiring layers each formed on the insulating layer to interconnect an associated one of the chip electrodes to a corresponding one of the ball electrodes; a second semiconductor chip stacked over the second surface of the first semiconductor chip; and a second seal that seals at least a first gap between the first and second semiconductor chips.
10. The device according to claim 9 , wherein the second semiconductor chip is greater in size than the first semiconductor chip.
11. The device according to claim 9 , further comprising: a plurality of second chip electrodes formed on the second main surface of the first semiconductor chip, the second chip electrodes being electrically connected to the first chip electrodes, wherein the second semiconductor chip includes a plurality of third chip electrodes formed on a fifth main surface thereof, the second semiconductor chip is stacked over the second main surface of the first semiconductor chip so that the third chip electrodes electrically connects to the second chip electrodes of the first semiconductor chip.
12. The device according to claim 11 , wherein the second semiconductor chip includes a plurality of fourth chip electrodes formed on a sixth main surface that is opposite to the fifth main surface, the fourth chip electrodes being electrically connected to the third electrodes.
13. A device comprising: a first semiconductor chip including a first main surface and a second main surface opposite to the first main surface, the first semiconductor chip further including a plurality of chip electrodes on a side of the first main surface; a first seal including a third main surface and a fourth main surface opposite to the third main surface, the first seal including a hole formed therein and being substantially the same in thickness as the first semiconductor chip to accommodate the first semiconductor chip in the hole such that the third main surface of the first seal is substantially coplanar with the first main surface of the first semiconductor chip and the fourth main surface of the first seal is substantially coplanar with the second main surface of the first semiconductor chip; an insulating layer formed in contact with the first main surface of the first semiconductor chip and with the third main surface of the first seal, the insulating layer including a plurality of holes that expose the chip electrodes of the first semiconductor chip, respectively; a plurality of ball electrodes formed over the insulating layer apart from the chip electrodes; a plurality of rewiring layers each formed on the insulating layer to interconnect an associated one of the chip electrodes to a corresponding one of the ball electrodes; and a chip stacked structure including a plurality of second semiconductor chips that are stacked on one another, the chip stacked structure including a plurality of bump electrodes on a lowermost one of the second semiconductor chips, and the chip stacked structure stacked over the second main surface of the first semiconductor chip, the bump electrodes being electrically connected to the chip electrodes of the first semiconductor chip.
14. The device according to claim 13 , wherein the plurality of second semiconductor chips include a plurality of through electrodes and the second semiconductor chips are electrically connected to one another via the through electrodes.
15. The device according to claim 13 , wherein the chip stacked structure includes a supporting substrate, the supporting substrate is stacked over an uppermost one of the second semiconductor chips, the second semiconductor chips being between the first semiconductor chip and the supporting substrate.
16. The device according to claim 9 , wherein the second semiconductor chip includes a fifth main surface facing the first semiconductor chip and a sixth main surface opposite to the fifth main surface, and the device further comprising: a third seal including a seventh main surface and a eighth main surface opposite to the seventh main surface, the third seal including a hole formed therein and being substantially the same in thickness as the second semiconductor chip to accommodate the second semiconductor chip in the hole such that the seventh main surface of the third seal is substantially coplanar with the fifth main surface of the second semiconductor chip and the eighth main surface of the third seal is substantially coplanar with the sixth main surface of the second semiconductor chip; a second insulating layer formed in contact with the sixth main surface of the second semiconductor chip and with the eighth main surface of the third seal, the second insulating layer including a plurality of holes that expose parts of the second semiconductor chip, respectively; a plurality of second chip electrodes each formed in associated one of the holes of the second insulating layer to be in contact with a corresponding one of the parts of the second semiconductor chip; a plurality of land electrodes formed over the second insulating layer apart from the second chip electrodes; and a plurality of second rewiring layers each formed on the second insulating layer to interconnect an associated one of the second chip electrodes to a corresponding one of the land electrodes.
17. The device according to claim 9 , wherein the first semiconductor chip is an interface chip or a logic chip, and the second semiconductor chip is a memory chip.
18. The semiconductor device according to claim 1 , wherein the second semiconductor chip is greater in size than the first semiconductor chip.
19. A device comprising: a first semiconductor chip including a first surface, a second surface opposite to the first surface, side surfaces joined to the first and second surfaces to define edges thereof, and a plurality of first electrodes formed on the second surface; a first sealing resin surrounding the side surfaces of the first semiconductor chip, the first sealing resin being in direct contact with the side surfaces of the first semiconductor chip and including a lower surface which is substantially coplanar with the second surface of the first semiconductor chip, the lower surface of the first sealing resin including a plurality of portions; an insulating layer formed in contact with the second surface of the first semiconductor chip and with the lower surface of the first sealing resin, the insulating layer including a plurality of holes that expose the first electrodes of the first semiconductor chip, respectively; a plurality of ball electrodes formed over the insulating layer apart from the first semiconductor chip, each of the ball electrodes being vertically aligned with an associated one of the portions of the lower surface of the first sealing resin; and a plurality of rewiring layers each connected to an associated one of the first electrodes through an associated one of the holes of the insulating layer and elongated over the insulating layer to reach a corresponding one of the ball electrodes; wherein the first semiconductor chip includes a plurality of second electrodes formed on the first surface, the plurality of second electrodes are electrically connected to the plurality of first electrodes, respectively.
20. The device according to claim 19 , further comprising: a second semiconductor chip stacked over the first surface of the first semiconductor chip.
21. The device according to claim 20 , further comprising: a second sealing resin that seals at least a first gap between the first and second semiconductor chips.
22. The device according to claim 19 , further comprising: a supporting substrate stacked over the first surface of the first semiconductor chip, the first semiconductor chip being disposed between the insulating layer and the supporting substrate.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
September 9, 2010
November 5, 2013
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