Disclosed is a semiconductor device which includes: a semiconductor element 200 including a first metal-insulator-semiconductor field-effect transistor 200a and a second metal-insulator-semiconductor field-effect transistor 200b which is connected in parallel with the first metal-insulator-semiconductor field-effect transistor; and a control section which controls the operation of the semiconductor element. The control section controls the semiconductor element so that in a forward direction mode, current flows in a forward direction through the first and second metal-insulator-semiconductor field-effect transistors but that in a reverse direction mode, current flows in the reverse direction through the first metal-insulator-semiconductor field-effect transistor but does not flow through the second metal-insulator-semiconductor field-effect transistor.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device comprising: a semiconductor element including a first metal-insulator-semiconductor field-effect transistor and a second metal-insulator-semiconductor field-effect transistor which is connected in parallel with the first metal-insulator-semiconductor field-effect transistor; and a control section which controls the operation of the semiconductor element, and wherein each of the first and second metal-insulator-semiconductor field-effect transistors includes: a source electrode; a drain electrode; a gate electrode; and a silicon carbide semiconductor layer which functions as a channel, and wherein the direction of current flowing from the drain electrode through the silicon carbide semiconductor layer toward the source electrode is defined to be a forward direction and the direction of current flowing from the source electrode through the silicon carbide semiconductor layer toward the drain electrode is defined to be a reverse direction, and wherein the control section is configured to control the semiconductor element so that in a forward direction mode, current flows in the forward direction through the first and second metal-insulator-semiconductor field-effect transistors but that in a reverse direction mode, current flows in the reverse direction through the first metal-insulator-semiconductor field-effect transistor and the amount of reverse current flowing through the second metal-insulator-semiconductor field-effect transistor becomes smaller than that of reverse current flowing through the first metal-insulator-semiconductor field-effect transistor.
2. The semiconductor device of claim 1 , wherein the first and second metal-insulator-semiconductor field-effect transistors have the same transistor characteristic.
3. The semiconductor device of claim 1 , wherein the potential of the gate electrode with respect to the source electrode is defined to be Vgs, and wherein the control section is configured so that in the reverse direction mode, the second metal-insulator-semiconductor field-effect transistor has a smaller Vgs than the first metal-insulator-semiconductor field-effect transistor.
4. The semiconductor device of claim 3 , wherein the control section is configured so that a difference in Vgs between the first and second metal-insulator-semiconductor field-effect transistors becomes equal to or greater than 2 V.
5. The semiconductor device of claim 4 , wherein the control section is configured so that Vgs of the first and second metal-insulator-semiconductor field-effect transistors both become negative values.
6. The semiconductor device of claim 5 , wherein the control section is configured so that a difference in Vgs between the first and second metal-insulator-semiconductor field-effect transistors becomes equal to or greater than 5 V.
7. The semiconductor device of claim 3 , wherein the control section is configured to set Vgs of the first and second metal-insulator-semiconductor field-effect transistors to be equal to 0 V and less than 0 V, respectively, in the reverse direction mode.
8. The semiconductor device of claim 1 , wherein the first and second metal-insulator-semiconductor field-effect transistors are arranged on mutually different substrates.
9. The semiconductor device of claim 1 , wherein the first and second metal-insulator-semiconductor field-effect transistors are arranged on the same substrate.
10. The semiconductor device of claim 1 , further comprising a terminal structure that surrounds the first and second metal-insulator-semiconductor field -effect transistors.
11. The semiconductor device of claim 1 , wherein the semiconductor element further includes a diode which is connected in series to the second metal-insulator-semiconductor field-effect transistor, and wherein the first metal-insulator-semiconductor field-effect transistor is connected in parallel with the second metal-insulator-semiconductor field-effect transistor and the diode that are connected in series together.
12. A power converter comprising a plurality of legs, each of which includes an upper arm and a lower arm that are each comprised of the semiconductor devices of claim 1 .
13. The power converter of claim 12 , wherein current flows through a smaller number of first and second metal-insulator-semiconductor field-effect transistors in the reverse direction mode than in the forward direction mode.
14. A method for controlling a semiconductor element including a first metal-insulator-semiconductor field-effect transistor and a second metal-insulator-semiconductor field-effect transistor which is connected in parallel with the first metal-insulator-semiconductor field-effect transistor, wherein each of the first and second metal-insulator-semiconductor field-effect transistors includes a source electrode, a drain electrode, a gate electrode, and a silicon carbide semiconductor layer which functions as a channel, and wherein the direction of current flowing from the drain electrode through the silicon carbide semiconductor layer toward the source electrode is defined to be a forward direction and the direction of current flowing from the source electrode through the silicon carbide semiconductor layer toward the drain electrode is defined to be a reverse direction, the method comprising: controlling the semiconductor element so that in a forward direction mode, current flows in the forward direction through the first and second metal-insulator-semiconductor field-effect transistors but that in a reverse direction mode, current flows in the reverse direction through the first metal-insulator-semiconductor field-effect transistor and the amount of reverse current flowing through the second metal-insulator-semiconductor field-effect transistor becomes smaller than that of reverse current flowing through the first metal-insulator-semiconductor field-effect transistor.
15. A method for controlling the power converter of claim 12 , the method comprising: driving the semiconductor elements of the upper and lower arms so as to alternately turn ON with a dead time, in which the semiconductor elements of the upper and lower arms are both turned OFF, interposed, and either the semiconductor element of the upper arm or the second metal-insulator-semiconductor field-effect transistor of the semiconductor element of the lower arm has its gate voltage set to be a negative voltage during at least a part of the dead time.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
April 16, 2012
November 12, 2013
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