A semiconductor device package includes a semiconductor device having connection pads formed thereon, with the connection pads being formed on first and second surfaces of the semiconductor device with edges of the semiconductor device extending therebetween. A first passivation layer is applied on the semiconductor device and a base dielectric laminate is affixed to the first surface of the semiconductor device that has a thickness greater than that of the first passivation layer. A second passivation layer having a thickness greater than that of the first passivation layer is applied over the first passivation layer and the semiconductor device to cover the second surface and the edges of the semiconductor device, and metal interconnects are coupled to the connection pads, with the metal interconnects extending through vias formed through the first and second passivation layers and the base dielectric laminate sheet to form a connection with the connection pads.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of forming a semiconductor device package comprising: providing a semiconductor device having a substrate composed of a semiconductor material and a plurality of metallic connection pads formed on the substrate, with the plurality of metallic connection pads being formed on top and bottom surfaces of the semiconductor device; applying a first passivation layer onto the top and bottom surfaces of the semiconductor device and onto edges of the semiconductor device extending between the top and bottom surfaces; adhering a base dielectric film to the bottom surface of the semiconductor device; applying a second passivation layer over the top surface and the edges of the semiconductor device and over the first passivation layer to form a passivated semiconductor device, the second passivation layer having a thickness greater than that of the first passivation layer; patterning the base dielectric film and the first and second passivation layers to expose the plurality of metal interconnects; and forming a plurality of metal interconnects that extend through the patterned base dielectric film or through the patterned first and second passivation layers to form a direct metallic connection with the plurality of metallic connection pads.
2. The method of claim 1 wherein applying the first passivation layer comprises applying one of a silicon nitride and silicon oxide film by way of a plasma enhanced chemical vapor deposition.
3. The method of claim 1 wherein applying the second passivation layer comprises applying at least one dielectric laminate sheet over the top surface and the edges of the semiconductor device, the at least one dielectric laminate sheet being applied so as to substantially match a shape of the semiconductor device.
4. The method of claim 3 further comprising filling in a void formed between the at least one dielectric laminate sheet and the semiconductor device with one of an epoxy and a polyimide.
5. The method of claim 1 wherein applying the second passivation layer comprises: spray coating a liquid dielectric material over the top surface and the edges of the semiconductor device; and curing the liquid dielectric material to form a dielectric layer on the semiconductor device.
6. The method of claim 1 wherein applying the second passivation layer comprises: positioning the semiconductor device within a mold; injecting a liquid dielectric material into a space between the semiconductor device and the mold; curing the liquid dielectric material to form a dielectric layer on the semiconductor device; and removing the semiconductor device and cured dielectric layer from the mold.
7. The method of claim 1 wherein applying the second passivation layer comprises: applying a liquid dielectric material onto the top surface and the edges of the semiconductor device in a selective manner so as to form a plurality of lines and dots of dielectric material; and curing the plurality of lines and dots of applied dielectric material to form a patterned dielectric layer on the semiconductor device.
8. The method of claim 1 further comprising trimming off a portion of the base dielectric film that extends out past a perimeter of the passivated semiconductor device by way of a laser ablation.
9. The method of claim 8 further comprising: applying an additional dielectric laminate sheet onto the bottom surface of the trimmed passivated semiconductor device, the additional dielectric laminate sheet extending out past a perimeter of the passivated semiconductor device; and forming a window in the additional dielectric laminate sheet in an area adjacent the passivated semiconductor device; wherein the plurality of metal interconnects extend from the top and bottom surfaces of the passivated semiconductor device and onto top and bottom surfaces of the additional dielectric laminate sheet.
10. The method of claim 9 further comprising: ablating through the additional dielectric laminate sheet in an area distal from the passivated semiconductor device and free of the plurality of metal interconnects; adhering another dielectric film over the top surface of the passivated semiconductor device, the another dielectric film extending out past perimeter of the passivated semiconductor device and being adhered to the additional dielectric laminate sheet applied on the bottom surface of the passivated semiconductor device; and ablating the another dielectric film in an area aligned with the ablated additional dielectric laminate sheet so as to form a lap joint.
11. The method of claim 10 further comprising: applying adhesive on the lap joint; adhering the semiconductor device package to another adjacent semiconductor device package by way of the adhesive on the lap joint; and electrically coupling the semiconductor device package to another adjacent semiconductor device package at the lap joint via one of a metal strip, a solder, or another conductive material.
12. The method of claim 1 wherein providing a semiconductor device comprises providing an optical diode configured to switch responsive to received light, and further comprising ablating a portion of the base dielectric film adjacent the semiconductor device to form an optical window that exposes the bottom surface of the optical diode and provides for light to be received thereby.
13. A method of forming a semiconductor device package comprising: providing a semiconductor device having a substrate composed of a semiconductor material and a plurality of metallic connection pads formed on the substrate, with the plurality of metallic connection pads being formed on top and bottom surfaces of the semiconductor device; applying a thin first passivation layer about the semiconductor device so as to passivate the top and bottom surfaces of the semiconductor device and passivate edges of the semiconductor device; applying a base dielectric laminate to the bottom surface of the semiconductor device; applying a second passivation layer over at least the edges of the semiconductor device and over the first passivation layer to form a passivated semiconductor device; patterning the base dielectric film and the first and second passivation layers to form a plurality of vias therethrough; and forming a plurality of metal interconnects that extend through the vias to form a direct metallic connection with the plurality of metal interconnects; wherein the second passivation layer is applied so as to have a thickness that provides a desired breakdown voltage for the semiconductor device package and that also provides a minimized parasitic inductance for the semiconductor device package.
14. The method of claim 13 wherein applying the second passivation layer comprises: applying at least one dielectric laminate sheet over the top surface and the edges of the semiconductor device, the at least one dielectric laminate sheet being applied so as to substantially match a shape of the semiconductor device; and filling in any voids formed between the at least one dielectric laminate sheet and the semiconductor device with one of an epoxy and a polyimide.
15. The method of claim 13 wherein applying the second passivation layer comprises applying a liquid dielectric material over the top surface and the edges of the semiconductor device via one of a spray application, a molding application, and a selective deposition application.
16. A method of forming a semiconductor device package comprising: providing a semiconductor device having a substrate composed of a semiconductor material and a plurality of metallic connection pads formed on the substrate, with the plurality of metallic connection pads being formed on top and bottom surfaces of the semiconductor device; applying a first passivation layer onto the top and bottom surfaces of the semiconductor device and onto edges of the semiconductor device extending between the top and bottom surfaces; adhering a base dielectric film to the bottom surface of the semiconductor device; applying a second passivation layer over the top surface and the edges of the semiconductor device and over the first passivation layer to form a passivated semiconductor device; applying an additional dielectric laminate sheet onto the bottom surface of the passivated semiconductor device so as to extend out past a perimeter thereof, the additional dielectric laminate sheet having a window in an area adjacent the passivated semiconductor device; patterning the base dielectric film and the first and second passivation layers to expose the plurality of metallic connection pads; and forming a plurality of metal interconnects that extend through the patterned first passivation layer or through the patterned base dielectric film and the patterned second passivation layer to form a direct metallic connection with the plurality of metallic connection pads.
17. The method of claim 16 wherein the second passivation layer is applied to have a thickness greater than the first passivation layer, so as to provide a desired breakdown voltage for the semiconductor device package and provide a minimized parasitic inductance for the semiconductor device package.
18. The method of claim 16 wherein applying the second passivation layer comprises: applying at least one dielectric laminate sheet over the over the top surface and the edges of the semiconductor device, the at least one dielectric laminate sheet being applied so as to substantially match a shape of the semiconductor device; and filling in any voids formed between the at least one dielectric laminate sheet and the semiconductor device with one of an epoxy and a polyimide.
19. The method of claim 16 further comprising: ablating through the additional dielectric laminate sheet in an area distal from the passivated semiconductor device and free of the plurality of metal interconnects; adhering another dielectric film over the top surface of the passivated semiconductor device, the another dielectric film extending out past perimeter of the passivated semiconductor device and being adhered to the additional dielectric laminate sheet applied on the bottom surface of the passivated semiconductor device; and ablating the another dielectric film in an area aligned with the ablated additional dielectric laminate sheet so as to form a lap joint.
20. The method of claim 19 further comprising: applying adhesive on the lap joint; adhering the semiconductor device package to another adjacent semiconductor device package by way of the adhesive on the lap joint; and electrically coupling the semiconductor device package to another adjacent semiconductor device package at the lap joint via one of a metal strip, a solder, or another conductive material.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
September 7, 2012
November 19, 2013
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