A method for fabricating a layer including nickel monosilicide NiSi on a substrate including silicon. The method includes the steps of incorporating, on a portion of the thickness of the substrate comprising silicon, an element selected from W, Ti, Ta, Mo, Cr and mixtures thereof; depositing, on the substrate, a layer of nickel and a layer of an element selected from Pt, Pd, Rh, and mixtures thereof or a layer comprising both nickel and an element selected from Pt, Pd, Rh, and mixtures thereof; heating to a temperature sufficient for obtaining the formation of a layer comprising nickel silicide optionally in the form of nickel monosilicide NiSi; incorporating fluorine in the layer; and optionally, heating to a sufficient temperature to convert the layer to a layer comprising nickel silicide entirely in the form of nickel monosilicide NiSi.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for fabricating a layer including nickel monosilicide NiSi on a substrate including silicon, the method comprising the following steps in succession: a) a step of incorporating, on a portion of a thickness of the substrate, an element selected from W, Ti, Ta, Mo, Cr, and mixtures thereof; b) a step of depositing, on the substrate obtained in step a), one of a first layer configuration and a second layer configuration, where the first layer configuration includes a layer of nickel and a layer of an element selected from Pt, Pd, Rh, and mixtures thereof, and where the second layer configuration includes a layer including both nickel and an element selected from Pt, Pd, Rh, and mixtures thereof; c) a step of heating the one of the first and second layer configurations to a temperature sufficient to form a layer including nickel silicide that forms optionally as nickel monosilicide NiSi; d) a step of incorporating fluorine in the layer including nickel silicide obtained in step c); and e) optionally, a step of heating the layer obtained in step d) to a temperature sufficient to convert the layer obtained in step d) to a layer including nickel silicide entirely formed of nickel monosilicide NiSi.
2. The method according to claim 1 , wherein step a) is carried out via ion implantation.
3. The method according to claim 1 , wherein the thickness of the substrate is between 10 nm and 40 nm.
4. The method according to claim 1 , wherein the element incorporated in step a) is present in a content between 0.05 and 1 atomic % of a total number of silicon atoms of the substrate.
5. The method according to claim 1 , wherein the element incorporated in step a) is tungsten.
6. The method according to any claim 1 , wherein nickel accounts for at least 90 atomic % of a total of atoms of the nickel and the elements selected from Pd, Pt, Rh, and mixtures thereof within the one of the first and second layer configurations obtained in step b).
7. The method according to claim 1 , wherein step b) is carried out at a temperature below 100° C.
8. The method according to claim 1 , wherein the heating step c) is carried out at a temperature between 200 and 600° C.
9. The method according to claim 1 , wherein step d) of incorporating fluorine is carried out via ion implantation.
10. A layer including nickel monosilicide NiSi disposed on a substrate including silicon, the layer comprising: an element selected from W, Ti, Ta, Mo, Cr, and mixtures thereof; an element selected from Pd, Pt, Rh, and mixtures thereof; and fluorine, wherein the layer is obtained via the method according to claim 1 .
11. The layer according to claim 10 , wherein the element selected from W, Ti, Ta, Mo, Cr, and mixtures thereof is present in a content between 0.05 and 1 atomic % of a total number of silicon atoms of the substrate.
12. The layer according to claim 10 , wherein the thickness of the substrate is between 10 nm and 40 nm.
13. The layer according to claim 10 , wherein nickel of the nickel monosilicide accounts for at least 90 atomic % of a total of atoms of the nickel and of the elements selected from Pd, Pt, Rh, and mixtures thereof within the one of the first and second layer configurations obtained in step b) in the method of claim 1 .
14. A method for fabricating an electronic device, the method comprising the following steps in succession: a step of preparing constituent elements of the electronic device, at least one of the constituent elements being in silicon; and a step of depositing, on each silicon constituent element, a layer including nickel monosilicide NiSi, the layer being obtained via the method according to claim 1 .
15. The method according to claim 14 , wherein the electronic device is an MOS transistor.
16. An electronic device comprising: at least one silicon constituent element; and a layer covering the at least one silicon constituent element, the layer including nickel monosilicide NiSi, and the layer being obtained via the method according to claim 1 , the layer including the element in step a) selected from W, Ti, Ta, Mo, Cr, and mixtures thereof, the element in step b) selected from Pd, Pt, Rh, and mixtures thereof; and fluorine.
17. The electronic device according to claim 16 , wherein the electronic device is an MOS transistor including a source, a drain, and a grid, and wherein the at least one silicon constituent element covered by the layer includes the source, the drain, and the grid.
18. A method for fabricating a three-dimensional integrated circuit of MOS type including transistors having different conductivities, the transistors being formed respectively in first and second superimposed semiconductor layers, the method comprising the following steps in succession: a step of fabricating a first level including at least one n-MOS type transistor including a source, a drain, and a grid, formed in a silicon semiconductor layer; a step of depositing a layer including nickel monosilicide on silicon portions of the at least one n-MOS type transistor, the silicon portions being the source, the drain, and the grid, the layer including nickel monosilicide NiSi being obtained via the method to claim 1 ; a step of transferring to the first level a germanium semiconductor layer, thereby constituting a second level on the first level; and a step of fabricating in the second level at least one p-MOS type transistor in the germanium semiconductor layer.
19. A three-dimensional integrated circuit of MOS type comprising: a first level including at least one n-MOS type transistor including a source, a drain, and a grid, formed in a silicon semiconductor layer; layers including nickel monosilicide NiSi disposed on silicon portions of the at least one n-MOS type transistor, the silicon portions being the source, the drain, and the grid, the layers being obtained via the method according to claim 1 , and the layers including the element in step a) selected from W, Ti, Ta, Mo, Cr, and mixtures thereof, the element in step b) selected from Pd, Pt, Rh, and mixtures thereof, and fluorine; and a second level on the first level including a germanium semiconductor layer including at least one p-MOS type transistor.
20. The method according to claim 1 , wherein the fluorine used in step d) decreases film resistance of the layer formed in step c).
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
November 5, 2009
November 19, 2013
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