In one embodiment, there is provided a semiconductor memory that includes: a semiconductor substrate having a channel region; a first tunnel insulating film on the channel region; a first fine particle layer on the first tunnel insulating film, the first fine particle layer including first conductive fine particles; a second tunnel insulating film on the first fine particle layer; a second fine particle layer on the second tunnel insulating film, the second fine particle layer including second conductive fine particles; a third tunnel insulating film on the second fine particle layer; a third fine particle layer on the third tunnel insulating film, the third fine particle layer including third conductive fine particles. A mean particle diameter of the second conductive fine particles is larger than that of the first conductive fine particles and that of the third conductive fine particles.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor memory comprising: a semiconductor substrate having a channel region; a first tunnel insulating film formed on the channel region of the semiconductor substrate; a first fine particle layer formed on the first tunnel insulating film, the first fine particle layer comprising a plurality of first conductive fine particles that meet a Coulomb blockade condition; a second tunnel insulating film formed on the first fine particle layer; a second fine particle layer formed on the second tunnel insulating film, the second fine particle layer comprising a plurality of second conductive fine particles that meet the Coulomb blockade condition, wherein a mean particle diameter of the second conductive fine particles is larger than that of the first conductive fine particles; a third tunnel insulating film formed on the second fine particle layer; a third fine particle layer formed on the third tunnel insulating film, and wherein the second fine particle layer is between the first fine particle layer and the third fine particle layer, the third fine particle layer comprising a plurality of third conductive fine particles that meet the Coulomb blockade condition, wherein a mean particle diameter of the third conductive fine particles is smaller than that of the second conductive fine particles; a fourth tunnel insulating film formed on the third fine particle layer; a charge storage film formed on the fourth tunnel insulating film; a block insulating film formed on the charge storage film; and a gate electrode formed on the block insulating film.
2. The semiconductor memory according to claim 1 , wherein the second tunnel insulating film or the third tunnel insulating film is formed to have a tunneling resistance that is lower than that of a silicon oxide film having a thickness of 2 nm.
3. The semiconductor memory according to claim 1 , wherein the first conductive fine particles, the second conductive fine particles and the third conductive fine particles are made of silicon nano-crystals.
4. The semiconductor memory according to claim 1 , wherein the first to fourth tunnel insulating films are made of silicon oxide films.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
March 14, 2012
November 19, 2013
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