An integrally packaged optronic integrated circuit device including an integrated circuit die containing at least one of a radiation emitter and radiation receiver and having a transparent packaging layer overlying a surface of the die, the transparent packaging layer having an opaque coating adjacent to edges of the layer.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A packaged optoelectronic chip comprising: (a) a die having a face, the die including at least one of a radiation emitter or a radiation receiver adjacent the face; (b) a transparent packaging layer having a major surface overlying the face of the die and an edge surface bounding the major surface, a first portion of the major surface being exposed at an exterior of the packaged chip; and (c) an opaque layer covering a second portion of the major surface of the transparent packaging layer adjacent the edge surface, such that the second portion is not exposed at an exterior of the packaged chip.
2. A packaged chip as claimed in claim 1 , wherein the opaque layer covers at least a portion of the edge surface of the transparent packaging layer.
3. A packaged chip as claimed in claim 1 wherein the face of the die is a front surface, and the at least one of the radiation emitter or a radiation receiver is disposed adjacent the front surface, and the packaged chip further comprises an insulating layer overlying a rear surface of the die remote from the front surface.
4. A packaged chip as claimed in claim 3 further comprising contacts overlying the insulating layer electrically connected to the die.
5. A packaged chip as claimed in 1 further comprising contacts electrically connected to the die.
6. A packaged chip as claimed in claim 5 wherein said contacts are solderable contacts.
7. A packaged chip as claimed in claim 1 wherein said at least one of a radiation emitter or a radiation receiver is an imaging device.
8. A packaged chip as claimed in claim 1 further comprising an array of microlenses operatively associated with the die.
9. A packaged chip as claimed in claim 8 wherein said microlenses are incorporated in said transparent packaging layer.
10. A packaged chip as claimed in claim 1 further comprising an optical grating operatively associated with the die.
11. A packaged chip as claimed in claim 10 wherein said optical grating is incorporated in said transparent packaging layer.
12. A packaged chip as claimed in claim 1 further comprising a wavelength-selective filter operatively associated with the die.
13. A packaged chip as claimed in claim 12 wherein said wavelength-selective filter is incorporated in said transparent packaging layer.
14. A packaged chip as claimed in claim 1 , wherein the die has edges extending away from the face, the transparent packaging layer extends beyond at least one of the die edges, and the opaque layer covers at least a portion of the transparent packaging layer between the at least one die edge and the at least one edge of the transparent packaging layer.
15. A packaged chip as claimed in claim 14 wherein the face of the die has a longest dimension and the major surface of the transparent packaging layer has a longest dimension which exceeds the longest dimension of the face of the die by no more than 20%.
16. A packaged chip as claimed in claim 15 wherein the longest dimension of the transparent packaging layer does not exceed the longest dimension of the die by more than 10%.
17. A packaged chip as claimed in claim 15 wherein the longest dimension of the transparent packaging layer does not exceed the longest dimension of the die by more than 5%.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
October 26, 2006
November 26, 2013
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