Multi-port memory devices and methods

1. An integrated circuit device, comprising: a first integrated circuit (IC) portion having a single memory port to access at least one memory array, the single port including a first set of address, control and data paths; and a second IC portion comprising at least a first memory port and a second memory port for providing access to the memory locations of the first IC portion through the single memory port of the first IC portion, wherein the single memory port of the first IC portion is different from the first memory port and the second memory port of the second IC portion.

2. The integrated circuit device of claim 1 , wherein: the single port of the first IC portion is selected from: a parallel memory port that transmits bits of a same data value in parallel with one another on separate signal lines, and a serial memory port that transmits bits of a same data value in on a same signal line.

3. The integrated circuit device of claim 1 , wherein: the first or second port of the second IC portion is selected from a parallel memory port that transmits bits of a same multi-bit data value in parallel with one another on separate signal lines, and a serial memory port that transmits bits of a same multi-bit data value in on a same signal line.

4. The integrated circuit device of claim 3 , wherein: the first and second ports of the second IC portion are parallel memory ports of different types.

5. The integrated circuit device of claim 1 , wherein: the second IC portion comprises programmable circuits configurable in response to configuration data to create communication paths between the first and second memory ports and the single port of the first IC portion.

6. The integrated circuit device of claim 1 , wherein: the first IC portion and second IC portion are part of the same monolithic integrated circuit.

7. The integrated circuit device of claim 1 , further including: the first IC portion is part of a first substrate; the second IC portion is part of a second substrate; and the first substrate and second substrate are electrically connected to one another in a same IC package.

8. The integrated circuit device of claim 1 , wherein: first IC portion includes a write data bus, a read data bus separate from the write data input, a write register coupled to the write data bus, a read data register coupled to the read data bus, a write address decoder coupled to an address bus that decodes write addresses, and a read address decoder coupled to the address bus that decodes read addresses.

9. A method, comprising: accessing a first integrated circuit (IC) portion, having at least one memory array accessed by a single port, with at least one second IC portion electrically coupled to the single port of the first IC portion, the second IC portion having at least a first memory port and a second memory port for accessing the memory array through the single port of the first IC portion, wherein the single port of the first IC portion is different from the first memory port and the second memory port of the second IC portion.

10. The method of claim 9 , further including: configuring programmable circuits in the second IC portion to create communication paths between the first and second memory ports and the single port of the first IC portion.

11. The method of claim 10 , further including: configuring the programmable circuits to include data processing circuits between the first and second memory ports and the single memory port.

12. The method of claim 10 , further including: configuring the programmable circuits to include data access control circuits between the first and second memory ports and the single memory port.

13. The method of claim 9 , wherein: the first IC portion includes single port memory circuits formed in a substrate; and the second IC portion is formed in the same substrate.

14. The method of claim 9 , wherein: the first IC portion includes single port memory circuits in a first substrate; the second IC portion is formed in a second substrate; and the first and second substrates are assembled in a same multi-die integrated circuit package.

15. The method of claim 9 , further including: the second portion comprises programmable circuits configured with configuration data generated from design data for a circuit that provides communication paths between at least the first memory port and the second memory port and the single port of the first IC portion; in a first type multi-port memory device, accessing the single port in at least one first IC portion through multiple ports in at least one second IC portion; and in a second type multi-port memory device, accessing the single port in at least another first IC portion through multiple ports in at least one third IC portion, the third IC portion having substantially non-programmable circuits designed with the design data.

16. A multi-port memory device, comprising: a single port memory integrated circuit portion (IC) that provides access to at least one memory array via a single port; and a multi-port IC portion having at least two memory ports that provide access to the single port of the single port memory IC portion, wherein the single port is different from the at least two memory ports.

17. The multi-port memory device of claim 16 , wherein: the multi-port IC portion comprises programmable circuits configurable to provide at least communication paths between the first and second memory ports and the single port in response to configuration information.

18. The multi-port memory device of claim 17 , wherein: the programmable circuits are configured to include data processing circuits between the first and second memory ports and the single port, the data processing circuits selected from: data encryption circuits that encrypt write data before writing such data into the single port memory IC portion, data decryption circuits that decrypt read data output from the single port memory IC portion, an error code generation circuit that generates error codes from data values of the single port memory IC portion, and an error correction circuit that error corrects data values of the single port memory IC portion based on corresponding error correction codes.

19. The multi-port memory device of claim 17 , further including: the programmable circuits are configured to include data access circuits between the first and second memory ports and the single port, the data access circuits selected from: authentication circuits that allow access to the single port memory IC portion based on comparing a received authentication value with a generated authentication value, partition circuits that logically divide that address space of the single port memory IC portion, built-in-self-test circuits, and redundancy circuits.

20. The multi-port memory device of claim 17 , wherein: the programmable circuits comprise a field programmable gate array architecture that includes at least one programmable logic core coupled to data lanes by programmable multiplexers and programmable de-multiplexers, and switch circuits for selectively connecting data lanes to one another.