A memory tag comprises an array of non-volatile memory, means for inductively obtaining power to enable receipt of data from and transmission of data to a reader device, a processor operable to process received data and to generate data to be transmitted; and a hash co-processor configured to apply a hash function to data applied to it. The array of non-volatile memory includes an area of write only memory. Reader devices for use with such memory tags and methods of using such memory tags are also described.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A memory-tag system comprising a memory-tag reader including: memory to store a duplicate authentication key, the duplicate authentication key being a duplicate of a device-authentication key stored by a memory tag; and a reader processor to, issue a read request to the memory tag, generate a current data-authentication key based on current data received from the memory tag in response to the read request and the duplicate authentication key, issue a data-authentication request to the memory tag, the data-authentication request specifying a random value, generate a reader hash digest based on a combination of the current data-authentication key and the random value, and determine whether the current data received represents altered or unaltered data based on a comparison of the reader hash digest with a tag hash digest received by the reader in response to the data-authentication request.
2. The memory-tag system as recited in claim 1 further comprising the memory tag, the memory tag including: a readable memory location for storing at times original data and the current data; a storage location to store the device-authentication key and an original data-authentication key; a tag processor to, in response to a write request from an external writer, store the original data in the readable memory location, and generate the original data-authentication key based on a combination of the original data and the device-authentication key.
3. The memory-tag system as recited in claim 2 wherein the tag processor is further to: respond to the read request from the memory-tag reader by providing the current data from the readable memory location to the memory-tag reader; and respond to the data-authentication request by generating the tag hash digest from a combination of the original data-authentication key and the random value.
4. A process comprising: making, by a memory-tag reader, a read request to a memory tag; generating, by the memory-tag reader, a current data-authentication key based on a combination of a duplicate of a device-authentication key stored by the memory tag and current data received from the memory tag in response to the read request; generating, by the memory-tag reader, a random value and a reader hash digest, the reader hash digest being generated based on a combination of the current data-authentication key and the random value; making, by the memory-tag reader to the memory tag, a data-authentication request including the random value; and in response to receiving a tag hash digest from the memory tag, determining whether the current data represents altered data or unaltered data based on a comparison of the tag and reader hash digests.
5. The process as recited in claim 4 further comprising generating, by the memory tag, the tag hash digest based on a combination of original data and an original data-authentication key generated and stored by the memory tag in response to data being written in response to a write request from a second reader device, the original data-authentication key being generated based on a combination of the device-authentication key and the original data.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
February 23, 2006
December 17, 2013
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