Leadframe-based semiconductor package

1. A semiconductor package, comprising: a leadframe comprising a die pad and a plurality of leads surrounding the die pad, the die pad having a top surface and an opposing bottom surface, and an opening being formed in the die pad; a carrier mounted to the bottom surface of the die pad, wherein a plurality of connecting pads are formed on the carrier, and a planar size of the carrier is greater than that of the die pad, allowing the connecting pads on a top surface of the carrier to be exposed from the die pad, wherein the leads are entirely located outside a vertical-forward projected area of the carrier, and the leads are free from being located inside the vertical-forward projected area of the carrier and free from contacting the carrier; at least a semiconductor chip attached to a side of an assembly comprising the die pad and the carrier, and electrically connected to the connecting pads of the carrier and the leads of the leadframe via bonding wires, wherein the semiconductor chip is placed in the opening of the die pad; and a package encapsulant encapsulating the semiconductor chip, the bonding wires, a part of the carrier and a part of the leadframe, allowing a bottom surface of the carrier and a part of the leads to be exposed from the package encapsulant.

2. The semiconductor package of claim 1 , wherein the plurality of connecting pads are formed on the top and bottom surfaces of the carrier, and the connecting pads on the top surface of the carrier are electrically connected to the bottom surface of the carrier via conductive structures formed in the carrier.

3. The semiconductor package of claim 1 , wherein an attaching pad is formed on the top surface of the carrier, allowing the die pad of the leadframe to be attached to the attaching pad.

4. The semiconductor package of claim 3 , wherein the attaching pad is electrically connected to the connecting pads on the bottom surface of the carrier via conductive structures formed in the carrier.

5. The semiconductor package of claim 3 , wherein the semiconductor chip is electrically connected to one of the die pad and the attaching pad via at least a grounding wire.

6. The semiconductor package of claim 3 , wherein the semiconductor chip is electrically connected to the die pad via at least a grounding wire, and the die pad is electrically connected to the attaching pad via at least another grounding wire.

7. The semiconductor package of claim 3 , wherein a planar size of the die pad of the leadframe is smaller than that of the semiconductor chip, and the semiconductor chip is electrically connected to the attaching pad of the carrier via at least a grounding wire.

8. The semiconductor package of claim 1 , wherein a distance between bottom surfaces of the leads of the leadframe and the bottom surface of the carrier is greater than a depth of a cavity of a mold for forming the package encapsulant.

9. The semiconductor package of claim 1 , wherein the semiconductor chip is attached to the top surface of the die pad.

10. The semiconductor package of claim 1 , wherein the semiconductor chip is attached to the top surface of the carrier.

11. The semiconductor package of claim 10 , wherein an attaching pad is formed on the top surface of the carrier, allowing the semiconductor chip to be attached to the attaching pad exposed within the opening of the die pad.

12. The semiconductor package of claim 11 , wherein the semiconductor chip is electrically connected via at least a grounding wire to the attaching pad exposed within the opening of the die pad.

13. The semiconductor package of claim 1 , wherein the carrier is covered with a soldermask layer, and the soldermask layer is formed with openings for exposing the connecting pads, allowing conductive components to be mounted to the connecting pads exposed within the openings of the soldermask layer.

14. The semiconductor package of claim 1 , wherein passive components are attached to and electrically connected to the connecting pads on the top surface of the carrier.

15. A semiconductor package, comprising: a leadframe comprising a die pad and a plurality of leads surrounding the die pad, the die pad having a top surface and an opposing bottom surface, and an opening being formed in the die pad; a carrier mounted to the bottom surface of the die pad, wherein a plurality of connecting pads are formed on the carrier, and a planar size of the carrier is greater than that of the die pad, allowing the connecting pads on a top surface of the carrier to be exposed from the die pad, wherein a bottom surface of the carrier is substantially flush with bottom surfaces of the leads, wherein the leads are entirely located outside a vertical-forward projected area of the carrier, and the leads are free from being located inside the vertical-forward projected area and free from contacting the carrier; at least a semiconductor chip attached to a side of an assembly comprising the die pad and the carrier, and electrically connected to the connecting pads of the carrier and the leads of the leadframe via bonding wires, wherein the semiconductor chip is placed in the opening of the die pad; and a package encapsulant encapsulating the semiconductor chip, the bonding wires, a part of the carrier and a part of the leadframe, allowing the bottom surface of the carrier and the bottom surfaces of the leads to be exposed from the package encapsulant.

16. The semiconductor package of claim 15 , wherein the leadframe is a quad flat non-leaded leadframe.

17. The semiconductor package of claim 15 , wherein the plurality of connecting pads are formed on the top and bottom surfaces of the carrier, and the connecting pads on the top surface of the carrier are electrically connected to the connecting pads on the bottom surface of the carrier via conductive structures formed in the carrier.

18. The semiconductor package of claim 15 , wherein an attaching pad is formed on the top surface of the carrier, allowing the die pad of the leadframe to be attached to the attaching pad.

19. The semiconductor package of claim 18 , wherein the attaching pad is electrically connected to the connecting pads on the bottom surface of the carrier via conductive structures formed in the carrier.

20. The semiconductor package of claim 18 , wherein the semiconductor chip is electrically connected to one of the die pad and the attaching pad via at least a grounding wire.

21. The semiconductor package of claim 18 , wherein the semiconductor chip is electrically connected to the die pad via at least a grounding wire, and the die pad is electrically connected to the attaching pad via at least another grounding wire.

22. The semiconductor package of claim 18 , wherein a planar size of the die pad of the leadframe is smaller than that of the semiconductor chip, and the semiconductor chip is electrically connected to the attaching pad of the carrier via at least a grounding wire.

23. The semiconductor package of claim 15 , wherein the semiconductor chip is attached to the top surface of the die pad.

24. The semiconductor package of claim 15 , wherein the semiconductor chip is attached to the top surface of the carrier.

25. The semiconductor package of claim 24 , wherein an attaching pad is formed on the top surface of the carrier, allowing the semiconductor chip to be attached to the attaching pad exposed within the opening of the die pad.

26. The semiconductor package of claim 25 , wherein the semiconductor chip is electrically connected via at least a grounding wire to the attaching pad exposed within the opening of the die pad.

27. The semiconductor package of claim 15 , wherein the carrier is covered with a soldermask layer, and the soldermask layer is formed with openings for exposing the connecting pads, allowing conductive components to be mounted to the connecting pads exposed within the openings of the soldermask layer.

28. The semiconductor package of claim 15 , wherein passive components are attached to and electrically connected to the connecting pad on the top surface of the carrier.