Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, wherein the carrier material comprises a top layer and a bottom layer separated by an etch stop layer; forming a dielectric material adjacent the die, forming a coreless substrate by building up layers on the dielectric material, and then removing the top layer carrier material and etch stop layer from the bottom layer carrier material.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method comprising; forming a cavity in a carrier material, wherein the carrier material comprises a top layer and a bottom layer separated by an etch stop layer; attaching a die in the cavity; forming a dielectric material adjacent the die and on the carrier material bottom layer; forming a coreless substrate by building up layers on the dielectric material; and removing the carrier material top layer and etch stop layer from the bottom layer of the carrier material.
2. The method of claim 1 further comprising wherein the bottom layer of the carrier material remains attached to the coreless substrate.
3. The method of claim 2 further comprising wherein the bottom layer of the carrier material comprises at least one of a heat spreader, an EMI shield structure, and a stiffener.
4. The method of claim 3 further comprising wherein the stiffener comprises a copper ring around the die.
5. The method of claim 1 further comprising removing the carrier material top layer and etch stop layer while they are disposed on the coreless substrate.
6. The method of claim 4 further comprising wherein the stiffener is attached to the substrate with no adhesive.
7. The method of claim 1 further comprising wherein the carrier material comprises copper.
8. The method of claim 1 further comprising wherein the coreless substrate comprises a portion of a coreless, bumpless, build up layer package.
9. A structure comprising: a die embedded in a coreless substrate; the coreless substrate including a dielectric material adjacent the die; die pad interconnect structures disposed in a die pad area of the die; and at least one functionalized carrier structure disposed within the coreless substrate, wherein a top surface of the at least one functionalized carrier structure is coplanar with a top surface of the coreless substrate and a back side of the microelectronic die.
10. The structure of claim 9 wherein the at least one functionalized structure comprises a copper material.
11. The structure of claim 9 wherein the coreless substrate comprises a portion of a coreless bumpless buildup package structure.
12. The structure of claim 9 wherein the at least one functionalized carrier structure comprises at least one of a stiffener, a heat spreader and an EMI shield.
13. The structure of claim 9 wherein the functionalized carrier structure is attached to the coreless package without an adhesive.
14. The structure of claim 13 wherein functionalized carrier structure comprises copper.
15. The structure of claim 11 wherein the die is fully embedded in the coreless substrate.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
April 16, 2010
December 31, 2013
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