A method includes extracting a first netlist from a first layout of a semiconductor circuit and estimating layout-dependent effect data based on the first netlist. A first simulation of the semiconductor circuit is performed based on the first netlist using an electronic design automation tool, and a second simulation of the semiconductor circuit is performed based on a circuit schematic using the electronic design automation tool. A weight and a sensitivity of the at least one layout-dependent effect are calculated, and the first layout of the semiconductor circuit is adjusted based on the weight and the sensitivity to provide a second layout of the semiconductor circuit. The second layout is stored in a non-transient storage medium.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method, comprising: extracting a first netlist from a first layout of a semiconductor circuit; estimating layout-dependent effect data based on the first netlist; performing a first simulation of the semiconductor circuit based on the first netlist using an electronic design automation tool; performing a second simulation of the semiconductor circuit based on a circuit schematic using the electronic design automation tool; calculating a weight and a sensitivity of the at least one layout-dependent effect; adjusting the first layout of the semiconductor circuit based on the weight and the sensitivity to provide a second layout of the semiconductor circuit; and storing the second layout in a non-transient storage medium.
2. The method of claim 1 , wherein the least one layout-dependent effect includes one of a well-proximity effect, an active area spacing effect, and a poly spacing effect.
3. The method of claim 1 , wherein estimating layout-dependent effect data includes categorizing a layout-dependent effect as one of a well-proximity effect, an active area spacing effect, and a poly spacing effect.
4. The method of claim 3 , further comprising calculating an impact of at least one layout-dependent effect based on the first and second simulation.
5. The method of claim 4 , wherein calculating the impact of at least one layout-dependent effect includes calculating a performance parameter of a device of the semiconductor circuit based on the second simulation; calculating the performance parameter of the device of the semiconductor circuit when subject to well-proximity effects; calculating the performance parameter of the device of the semiconductor circuit when subject to active area spacing effects; calculating the performance parameter of the device of the semiconductor circuit when subject to poly spacing effects; and normalizing the performance parameters of the device when subject to well-proximity effects, active area spacing effects, and poly spacing effects to the performance parameter of the device based on the second simulation.
6. The method of claim 4 , wherein calculating the impact of at least one layout-dependent effect includes: generating a contour map identifying at least one stress attributable to at least one layout-dependent effect; and displaying the contour map to a user on a display.
7. The method of claim 1 , wherein calculating the weight of the at least one layout-dependent effect includes: deriving a function for a first layout-dependent effect, the function approximating a performance parameter of a device of the semiconductor circuit based on a first set of physical parameters identified by the first layout; and deriving a function for a second layout-dependent effect, the function approximating a performance parameter of the device of the semiconductor circuit based on a second set of physical parameters identified by the first layout; and calculating a ratio of the function for the first layout-dependent effect relative to a sum of the function for the first layout-dependent effect and the function for the second layout-dependent effect.
8. A system, comprising: an electronic design automation tool including a processor configured to: provide a first netlist from a first layout of a semiconductor circuit; estimate layout-dependent effect data from the first netlist; perform a first simulation of the semiconductor circuit based on the first netlist and a second simulation of the semiconductor circuit based on a circuit schematic; calculate a weight and a sensitivity of the at least one layout-dependent effect; and adjust the first layout of the semiconductor circuit based on the weight and the sensitivity to provide a second layout of the semiconductor circuit.
9. The system of claim 8 , wherein the least one layout-dependent effect includes one of a well-proximity effect, an active area spacing effect, and a poly spacing effect.
10. The system of claim 8 , wherein when the processor is configured to categorize a layout-dependent effect as one of a well-proximity effect, an active area spacing effect, and a poly spacing effect when the processor extracts layout-dependent effect data.
11. The system of claim 10 , wherein the processor is configured to calculate an impact of at least one layout-dependent effect based on the first and second simulations, wherein the impact calculation includes a calculation of a performance parameter of a device of the semiconductor circuit based on the second simulation; a calculation of a the performance parameter of the device of the semiconductor circuit when subject to well-proximity effects; a calculation of the performance parameter of the device of the semiconductor circuit when subject to active area spacing effects; and a calculation the performance parameter of the device of the semiconductor circuit when subject to poly spacing effects when the processor calculates the impact of the at least one layout-dependent effect.
12. The system of claim 11 , wherein the processor is configured to normalize the performance parameters of the device when the device is subject to well-proximity effects, active area spacing effects, and poly spacing effects to the performance parameter of the device based on the second simulation.
13. The system of claim 12 , wherein the processor is configured to: generate a contour map identifying at least one stress attributable to at least one layout-dependent effect; and display the contour map to a user on a display of the system.
14. The system of claim 8 , wherein when calculating the weight of the at least one layout-dependent effect, the processor is configured to: derive a function for a first layout-dependent effect, the function approximating a performance parameter of a device of the semiconductor circuit based on a first set of physical parameters identified by the first layout; and derive a function for a second layout-dependent effect, the function approximating a performance parameter of the device of the semiconductor circuit based on a second set of physical parameters identified by the first layout; and calculate a ratio of the function for the first layout-dependent effect relative to a sum of the function for the first layout-dependent effect and the function for the second layout-dependent effect.
15. A non-transient storage medium encoded with program code, wherein when the program code is executed by a processor, the processor performs a method, the method comprising: extracting a first netlist from a first layout of a semiconductor circuit; estimating layout-dependent effect data from the first netlist; performing a first simulation of the semiconductor circuit based on the first netlist using an electronic design automation tool; performing a second simulation of the semiconductor circuit based on a circuit schematic using the electronic design automation tool; calculating a weight and a sensitivity of the at least one layout-dependent effect; adjusting the first layout of the semiconductor circuit based on the weight and the sensitivity to provide a second layout of the semiconductor circuit; and storing the second layout in a non-transient storage medium.
16. The non-transient storage medium of claim 15 , wherein extracting layout-dependent effect data includes categorizing a layout-dependent effect as one of a well-proximity effect, an active area spacing effect, and a poly spacing effect.
17. The non-transient storage medium of claim 16 , further comprising calculating an impact of at least one layout-dependent effect.
18. The non-transient computer readable storage medium of claim 17 , wherein calculating the impact of at least one layout-dependent effect includes calculating a performance parameter of a device of the semiconductor circuit based on the second simulation; calculating the performance parameter of the device of the semiconductor circuit when subject to well-proximity effects; calculating the performance parameter of the device of the semiconductor circuit when subject to active area spacing effects; calculating the performance parameter of the device of the semiconductor circuit when subject to poly spacing effects; and normalizing the performance parameters of the device when subject to well-proximity effects, active area spacing effects, and poly spacing effects to the performance parameter of the device based on the second simulation.
19. The non-transient computer readable storage medium of claim 18 , wherein calculating the impact of at least one layout-dependent effect includes: generating a contour map identifying at least one stress attributable to at least one layout-dependent effect; and displaying the contour map to a user on a display.
20. The non-transient computer readable storage medium of claim 15 , wherein calculating the weight of the at least one layout-dependent effect includes: deriving a function for a first layout-dependent effect, the function approximating a performance parameter of a device of the semiconductor circuit based on a first set of physical parameters identified by the first layout; and deriving a function for a second layout-dependent effect, the function approximating a performance parameter of the device of the semiconductor circuit based on a second set of physical parameters identified by the first layout; and calculating a ratio of the function for the first layout-dependent effect relative to a sum of the function for the first layout-dependent effect and the function for the second layout-dependent effect.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
April 30, 2012
December 31, 2013
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