A method and apparatus used within memory and data processing that reduces the number of references allowed in processor cache by using active rows to reject references that are less frequently used from the cache. Comparators within a memory controller are used to generate a signal indicative of a row hit or miss, which signal is then applied to one or more demultiplexers to enable or disable transfer of a memory reference to processor cache locations. The cache may be level one (L1) or level two (L2) caches including data and or instructions or some combination of L1, L2, data, and instructions.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of cache filtering, said method comprising: upon a cache miss, obtaining a row hit/miss signal associated with a bank of a main memory for a given memory reference; and rejecting said memory reference associated with said row hit/miss signal from the cache when said row hit/miss signal indicates a row miss.
2. The method as claimed in claim 1 , further comprising transferring to memory cache said memory reference associated with said row hit/miss signal when said row hit/miss signal indicates a row hit.
3. The method as claimed in claim 2 , wherein said transferring includes updating both level one cache and level two cache with said memory reference.
4. The method as claimed in claim 1 , wherein a row miss signal corresponds to a first access to a location in the DRAM.
5. A method of cache filtering within a main memory, said method comprising: generating a row hit/miss signal associated with a bank of the main memory corresponding to a memory reference; and upon occurrence of level one (L1) and level two (L2) cache misses and where said row hit/miss signal indicates a row miss, accessing data in said main memory using random access mode and latching a row corresponding to said data.
6. The method as claimed in claim 5 , further comprising transferring said data only to a register file.
7. The method as claimed in claim 6 , further comprising, upon occurrence of L1 and L2 cache misses and where said row hit/miss signal indicates a row hit, accessing data in said DRAM using open page mode, updating L1 and L2 cache, and maintaining as active said row corresponding to said data.
8. The method as claimed in claim 5 , wherein a row miss signal corresponds to a first access to a location in the DRAM.
9. An apparatus for data processing, said apparatus comprising: a main memory having a plurality of locations; a memory controller coupled to said main memory, said memory controller including at least one comparator for generating a row hit/miss signal corresponding to a memory reference related to one of said plurality of locations; at least one demultiplexer operatively coupled to said memory controller where said row hit/miss signal is used by said demultiplexer so as to route data related to said memory reference; and row latches for latching a row corresponding to said data.
10. The apparatus as claimed in claim 9 wherein said at least one demultiplexer is also operatively coupled to both level one (L1) and level two (L2) caches of a processor.
11. The apparatus as claimed in claim 10 further including a second demultiplexer operatively coupled to an L1 instruction cache of said processor, where said row hit/miss signal is used by said second demultiplexer so as to route instruction related to said memory reference and another row latch latches a row corresponding to an instruction row address.
12. The apparatus as claimed in claim 9 wherein said at least one demultiplexer is also operatively coupled only to level one (L1) cache of a processor and without regard to level two (L2) cache of said processor.
13. A method of cache filtering within a main memory comprising Static Random Access Memory (SRAM), said method comprising: generating a row hit/miss signal associated with a bank of the SRAM and corresponding to a memory reference; upon occurrence of level one (L1) and level two (L2) cache misses and where said row hit/miss signal indicates a row miss, accessing data in said SRAM using random access mode and latching a row corresponding to said data.
14. The method as claimed in claim 13 , further comprising transferring said data only to a register file.
15. The method as claimed in claim 14 , further comprising, upon occurrence of L1 and L2 cache misses and where said row hit/miss signal indicates a row hit, accessing data in said SRAM using open page mode, updating L1 and L2 cache, and maintaining as active said row corresponding to said data.
16. The method as claimed in claim 13 , wherein a row miss signal corresponds to a first access to a location in the SRAM.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
September 16, 2008
January 7, 2014
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