A low-defect gallium nitride structure including a first gallium nitride layer comprising a plurality of gallium nitride columns etched into the first gallium nitride layer and a first dislocation density; and a second gallium nitride layer that extends over the gallium nitride columns and comprises a second dislocation density, wherein the second dislocation density may be lower than the first dislocation density. In addition, a method for fabricating a gallium nitride semiconductor layer that includes masking an underlying gallium nitride layer with a mask that comprises an array of columns and growing the underlying gallium nitride layer through the columns and onto said mask using metal-organic chemical vapor deposition pendeo-epitaxy to thereby form a pendeo-epitaxial gallium nitride layer coalesced on said mask to form a continuous pendeo-epitaxial monocrystalline gallium nitride semiconductor layer.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A gallium nitride semiconductor device comprising: a first gallium nitride layer comprising a plurality of gallium nitride columns and trenches etched into said first gallium nitride layer and a first dislocation density; a second gallium nitride layer that comprises of two regions, a first region that is adjacent to the side walls of the gallium nitride columns further comprising a second layer of regions with a low and a high dislocation density having a low dislocation density and a second region that extends over said gallium nitride columns and comprises a higher dislocation density than the dislocation density of the first region; wherein on top of the second gallium nitride layer that comprises a low defect density region over trenches there is a Schottky contact, said Schottky contact comprised of about 500 Å of nickel and about 1,500 Å of gold; the device further comprising vertically aligned active regions of a semiconductor lateral device with the low defect density regions of the second gallium nitride layer, wherein said semiconductor lateral device extends beyond a top of two or more columns ( 5 ) and has multiple active regions wherein each active region is aligned so that a current flows only in the low defect density regions; wherein said semiconductor device active regions are between an edge of a Source (S) and an edge of a Drain (D), and further wherein the Source (S) edge and Drain (D) are positioned so that the current flows only in low defect density regions; wherein the current flows only in areas of low defect density and Source (S), Gate (G), and Drain (D) are on one plane, on a top of the device; and further wherein said gate ( 20 ) finger ( 20 a ) is within and on a top of the low defect density region.
2. The device of claim 1 , wherein said first gallium nitride layer of the device is vertically aligned over said second gallium nitride layer.
3. The device of claim 1 , wherein each of said plurality of gallium nitride columns are from about 1 μm to about 200 μm wide.
4. The device of claim 1 , wherein each of said plurality of gallium nitride columns are separated by a distance of at least one of 1 μm.
5. A semiconductor device comprising: a substrate; a plurality of gallium nitride columns coupled to said substrate; a plurality of gallium nitride trenches, coupled to said substrate, wherein each of said plurality of gallium nitride columns are positioned alternate with each of said plurality of gallium nitride trenches; a low defect density region in the second gallium nitride layer formed over said gallium nitride trenches; and an active region of a transistor the device further comprising vertical aligned active regions of a semiconductor lateral device with the low defect density regions of the second gallium nitride layer, wherein said semiconductor lateral device extends beyond a top of two or more columns ( 5 ) and has multiple active regions wherein each active region is aligned so that a current flows only in the low defect density regions; wherein said semiconductor device active regions are between an edge of a Source (S) and an edge of a Drain (D), and further wherein the Source (S) edge and Drain (D) are positioned so that the current flows only in low defect density regions; wherein the current flows only in areas of low defect density and Source (S), Gate (G), and Drain (D) are on one plane, on a top of the device; and further herein said gate ( 20 ) finger ( 20 a ) is within and on a top of the low defect density region.
6. The semiconductor device of claim 5 , wherein a Source (S) and a Detrain (D) comprise an ohmic contact and a Gate (G) comprises a Schottky contact.
7. The semiconductor device of claim 5 , wherein said substrate comprises at least one of sapphire and gallium nitride.
8. The semiconductor device of claim 5 , wherein said plurality of gallium nitride columns and said plurality of gallium nitride trenches are etched from a gallium nitride layer comprising both front and backside alignment marks for photolithography.
9. The semiconductor device of claim 5 , wherein said low defect density gallium nitride layer is formed over said gallium nitride columns using pendeo epitaxy.
10. The semiconductor device of claim 9 , wherein said low defect density gallium nitride layer comprises a first defect density region formed over each of said plurality of gallium nitride columns and a second defect density region formed over each of said plurality of gallium nitride trenches, and wherein said first defect density region is higher than said second defect density region.
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August 7, 2012
January 28, 2014
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