Fabricating semiconductor nanowires (5) on a substrate (1) having a metallic oxide layer (2), includes: a) exposing the metallic oxide layer to a hydrogen plasma (11) of power P for a duration t suitable for reducing the layer and for forming metallic nanodrops (3) of radius (Rm) on the surface of the metallic oxide layer; b) low temperature plasma-assisted deposition of a thin layer (4) of a semiconductor material on the metallic oxide layer including the metallic nanodrops, the thin layer having a thickness (Ha) suitable for covering the metallic nanodrops; and c) thermal annealing at a temperature T sufficient to activate lateral growth of nanowires by catalysis of the material deposited as a thin layer from the metallic nanodrops. Nanowires are obtained by this method and nanometric transistors including a semiconductor nanowire.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of fabricating semiconductor nanowires ( 5 ) on a substrate ( 1 ) including a metallic oxide layer ( 2 ), said semiconductor nanowires ( 5 ) extending on the surface of said substrate ( 1 ), comprising the following steps: a) exposing the metallic oxide layer ( 2 ) to a hydrogen plasma ( 11 ) of power P for a duration t suitable for reducing the layer ( 2 ) and for forming metallic nanodrops ( 3 ) of radius (Rm) on the surface of the metallic oxide layer ( 2 ); b) low temperature plasma-assisted deposition of a thin layer ( 4 ) of a semiconductor material on the metallic oxide layer ( 2 ) including the metallic nanodrops ( 3 ), said thin layer ( 4 ) having a thickness (Ha) suitable for covering the metallic nanodrops ( 3 ); and c) thermal annealing under vacuum at a temperature T higher than or equal to the melting temperature of the metallic nanodrops ( 3 ) so as to activate lateral growth of semiconductor nanowires ( 5 ) by catalysis of the semiconductor material deposited as a thin layer ( 4 ) from the metallic nanodrops ( 3 ) said lateral growth of said semiconductor nanowires ( 5 ) extending on the surface of said substrate ( 1 ) and being guided along the surface of the substrate, wherein the method includes a step of forming a guide prior to the thermal annealing step c), the lateral growth of the semiconductor nanowires ( 5 ) being guided along said guide along a predefined path and wherein forming the guide includes forming a channel ( 21 ) of semiconductor material, said channel forming said guide.
2. The method of fabricating nanowires ( 5 ) according to claim 1 , wherein the step of forming the guide includes forming a step ( 23 ) on the substrate ( 1 ), said step ( 23 ) having a lateral wall ( 24 ) and forming said guide means.
3. A method of fabricating semiconductor nanowires ( 5 ) on a substrate ( 1 ) including a metallic oxide layer ( 2 ), said semiconductor nanowires ( 5 ) extending on the surface of said substrate ( 1 ), comprising the following steps: a) exposing the metallic oxide layer ( 2 ) to a hydrogen plasma ( 11 ) of power P for a duration t suitable for reducing the layer ( 2 ) and for forming metallic nanodrops ( 3 ) of radius (Rm) on the surface of the metallic oxide layer ( 2 ); b) low temperature plasma-assisted deposition of a thin layer ( 4 ) of a semiconductor material on the metallic oxide layer ( 2 ) including the metallic nanodrops ( 3 ), said thin layer ( 4 ) having a thickness (Ha) suitable for covering the metallic nanodrops ( 3 ); and c) thermal annealing under vacuum at a temperature T higher than or equal to the melting temperature of the metallic nanodrops ( 3 ) so as to activate lateral growth of semiconductor nanowires ( 5 ) by catalysis of the semiconductor material deposited as a thin layer ( 4 ) from the metallic nanodrops ( 3 ) said lateral growth of said semiconductor nanowires ( 5 ) extending on the surface of said substrate ( 1 ) and being guided along the surface of the substrate, wherein the method includes a step of forming a guide prior to the thermal annealing step c), the lateral growth of the semiconductor nanowires ( 5 ) being guided along said guide along a predefined path, wherein the step of forming the guide includes forming a step ( 23 ) on the substrate ( 1 ), said step ( 23 ) having a lateral wall ( 24 ) and forming said guide means, wherein the semiconductor nanowires grow laterally along the step at the junction formed between the lateral wall and the surface of the substrate, and wherein the method includes, between step a) and step b), a step of depositing a layer ( 33 ) of dielectric material, followed by a step of etching said layer of dielectric material ( 33 ) to form said step ( 23 ) in said layer of dielectric material ( 33 ).
4. A method of fabricating an electronic device including a substrate ( 1 ) according to claim 1 , the method comprising the following steps: d) forming a layer ( 2 ) of metallic oxide on said substrate ( 1 ) so as to define a region ( 34 ) for initiating growth of semiconductor nanowires; e) forming one or more guide means for the growth of semiconductor nanowires ( 5 ), each guide means connecting the semiconductor nanowire growth initiation region ( 34 ) to a region ( 35 ) for ending semiconductor nanowire growth so as to define a functional path; and f) fabricating one or more semiconductor nanowires ( 5 ) in application of steps a), b), and c) so as to implement guided growth of semiconductor nanowires ( 5 ) along respective guide means during step c), each semiconductor nanowire ( 5 ) initiating its growth in the semiconductor nanowire growth initiation region ( 34 ) and continuing its growth to the semiconductor nanowire growth end region ( 35 ).
5. A method of fabricating an electronic device comprising semiconductor nanowires ( 5 ) on a substrate ( 1 ) including a metallic oxide layer ( 2 ), said semiconductor nanowires ( 5 ) extending on the surface of said substrate ( 1 ), comprising the following steps: a) exposing the metallic oxide layer ( 2 ) to a hydrogen plasma ( 11 ) of power P for a duration t suitable for reducing the layer ( 2 ) and for forming metallic nanodrops ( 3 ) of radius (Rm) on the surface of the metallic oxide layer ( 2 ); b) low temperature plasma-assisted deposition of a thin layer ( 4 ) of a semiconductor material on the metallic oxide layer ( 2 ) including the metallic nanodrops ( 3 ), said thin layer ( 4 ) having a thickness (Ha) suitable for covering the metallic nanodrops ( 3 ); and c) thermal annealing under vacuum at a temperature T higher than or equal to the melting temperature of the metallic nanodrops ( 3 ) so as to activate lateral growth of semiconductor nanowires ( 5 ) by catalysis of the semiconductor material deposited as a thin layer ( 4 ) from the metallic nanodrops ( 3 ) said lateral growth of said semiconductor nanowires ( 5 ) extending on the surface of said substrate ( 1 ) and being guided along the surface of the substrate; d) forming a layer ( 2 ) of metallic oxide on said substrate ( 1 ) so as to define a region ( 34 ) for initiating growth of semiconductor nanowires; e) forming one or more guide means for the growth of semiconductor nanowires ( 5 ), each guide means connecting the semiconductor nanowire growth initiation region ( 34 ) to a region ( 35 ) for ending semiconductor nanowire growth so as to define a functional path; and f) fabricating one or more semiconductor nanowires ( 5 ) in application of steps a), b), and c) so as to implement guided growth of semiconductor nanowires ( 5 ) along respective guide means during step c), each semiconductor nanowire ( 5 ) initiating its growth in the semiconductor nanowire growth initiation region ( 34 ) and continuing its growth to the semiconductor nanowire growth end region ( 35 ), and wherein during step e), between steps a) and b) a step is performed of depositing a layer ( 33 ) of dielectric material on the substrate ( 1 ) and the layer ( 2 ) of metallic oxide, this step of depositing a dielectric material layer ( 33 ) being followed by a step of etching said dielectric material ( 33 ) to form a step ( 23 ) in said dielectric material layer ( 33 ), said step ( 23 ) forming the guide means for the growth of semiconductor nanowires ( 5 ) wherein the semiconductor nanowires grow laterally along the step at the junction formed between the lateral wall and the surface of the substrate.
6. A nanometric transistor ( 20 ) based on one or more semiconductor nanowires ( 5 ) obtained by the method according to claim 1 , one of the nanowires ( 5 ) being suitable for forming a semiconductive connection between a source ( 16 ), a drain ( 17 ), and a gate ( 18 ) of said transistor.
10. The method of fabricating semiconductor nanowires ( 5 ) according to claim 1 , wherein the semiconductor material deposited as a thin layer ( 4 ) is selected from silicon (Si), germanium (Ge), carbon (C), or an alloy of these materials (SiGe, SiC, or SiGeC), said semiconductor material being deposited in amorphous, micro- or poly-crystalline form.
11. The method of fabricating silicon nanowires ( 5 ) according to claim 10 , wherein the material of the layer ( 4 ) is hydrogenated amorphous silicon (a-Si:H) having a thickness (Ha).
12. The method of fabricating carbon nanowires ( 5 ) according to claim 10 , wherein the material of the layer ( 4 ) is hydrogenated amorphous carbon (a-C:H) having a thickness (Ha).
13. The method of fabricating nanowires ( 5 ) according to claim 10 , wherein the metallic oxide ( 2 ) is an oxide of indium (InO), of tin (SnO2), of zinc (ZnO), of indium tin alloy (ITO), or a multilayer system of ZnO/ITO or ZnO/SnO2.
14. The method of fabricating nanowires ( 5 ) according to claim 1 , wherein the radius (Rm) of the metallic nanodrops ( 3 ) is known and the duration of deposition of the semiconductor layer ( 4 ) is determined in such a manner as to obtain a predetermined ratio ρ between the thickness (Ha) of the deposited layer ( 4 ) and the radius (Rm), the ratio ρ being suitable for ensuring lateral growth of the nanowires ( 5 ).
15. The method of fabricating nanowires ( 5 ) according to claim 14 , wherein the predetermined ratio η is equal to 1 so that a morphology of the nanowires ( 5 ) is rectilinear over a length lying in a range of ten times a diameter of the nanowire ( 5 ) to more than 100 times the diameter of the nanowire ( 5 ).
16. The method of fabricating nanowires ( 5 ) according to claim 1 , wherein the method further comprises a step of locally masking the metallic oxide layer ( 2 ) so as to form electrodes ( 14 , 15 ), and in that the growth of a nanowire ( 5 ) is performed between two electrodes ( 14 , 15 ).
17. A method of fabricating an electronic device including a substrate ( 1 ) according to claim 3 , the method comprising the following steps: d) forming a layer ( 2 ) of metallic oxide on said substrate ( 1 ) so as to define a region ( 34 ) for initiating growth of semiconductor nanowires; e) forming one or more guide means for the growth of semiconductor nanowires ( 5 ), each guide means connecting the semiconductor nanowire growth initiation region ( 34 ) to a region ( 35 ) for ending semiconductor nanowire growth so as to define a functional path; and f) fabricating one or more semiconductor nanowires ( 5 ) in application of steps a), b), and c) so as to implement guided growth of semiconductor nanowires ( 5 ) along respective guide means during step c), each semiconductor nanowire ( 5 ) initiating its growth in the semiconductor nanowire growth initiation region ( 34 ) and continuing its growth to the semiconductor nanowire growth end region ( 35 ).
18. A nanometric transistor ( 20 ) based on one or more semiconductor nanowires ( 5 ) obtained by the method according to claim 3 , one of the nanowires ( 5 ) being suitable for forming a semiconductive connection between a source ( 16 ), a drain ( 17 ), and a gate ( 18 ) of said transistor.
19. A nanometric transistor ( 20 ) based on one or more semiconductor nanowires ( 5 ) obtained by the method according to claim 5 , one of the nanowires ( 5 ) being suitable for forming a semiconductive connection between a source ( 16 ), a drain ( 17 ), and a gate ( 18 ) of said transistor.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
October 9, 2009
February 18, 2014
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.