A three-dimensional (3D) high density memory array includes multiple layers of segmented bit lines (i.e., sense lines) with segment switch devices within the memory array that connect the segments to global bit lines. The segment switch devices reside on one or more layers of the integrated circuit, preferably residing on each bit line layer. The global bit lines reside preferably on one layer below the memory array, but may reside on more than one layer. The bit line segments preferably share vertical connections to an associated global bit line. In certain EEPROM embodiments, the array includes multiple layers of segmented bit lines with segment connection switches on multiple layers and shared vertical connections to a global bit line layer. Such memory arrays may be realized with much less write-disturb effects for half selected memory cells, and may be realized with a much smaller block of cells to be erased.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A monolithic integrated circuit comprising: a three-dimensional memory array having at least two memory planes stacked one above the other, each memory plane comprising a respective plurality of segmented array lines of a first type and further comprising a respective plurality of segment switch devices, the three-dimensional memory array comprising a plurality of sub-arrays; a plurality of global bit line circuits each shared by a respective pair of adjacent sub-arrays, but disposed substantially beneath only one of the pair of adjacent sub-arrays; and a plurality of global array lines on at least one layer of the memory array; each segment switch device for coupling a segmented array line of the first type to an associated global array line, and each global array line being coupled to a respective segment switch device within each respective memory plane.
2. The integrated circuit of claim 1 further comprising a plurality of shared vertical connections in the memory array, each coupling at least two segment switch devices to an associated global array line.
3. The integrated circuit of claim 1 further comprising a plurality of shared vertical connections in the memory array, each coupling a respective segment switch device disposed within each of at least two respective memory planes to an associated global array line.
4. The integrated circuit of claim 1 wherein the global array lines run generally parallel to the segmented array lines of the first type.
5. The integrated circuit of claim 1 wherein the respective plurality of segmented array lines of the first type on at least two memory array layers are different in number.
6. The integrated circuit of claim 1 wherein a respective plurality of segment switch devices on at least two memory planes are different in number.
7. The integrated circuit of claim 1 wherein the plurality of segmented array lines of the first type on at least one memory array layer is different in number than the plurality of segment switch devices on at least one layer of the memory array.
8. The integrated circuit of claim 1 comprising EEPROM memory cells.
9. The integrated circuit of claim 1 comprising more than one type of memory cells within the three-dimensional memory array.
10. The integrated circuit of claim 1 further comprising: a respective plurality of bias segment lines on each of at least one memory array layer, each associated with at least one segmented array line of the first type on the same memory array layer.
11. The integrated circuit of claim 1 wherein array lines on at least one given array line layer are associated with memory cells that are also associated with array lines on a vertically adjacent array line layer above the given array line layer, and also associated with other memory cells that are associated with array lines on a vertically adjacent array line layer below the given array line layer.
12. The integrated circuit of claim 1 comprising passive element memory cells.
13. The integrated circuit of claim 12 comprising anti-fuse memory cells.
14. The integrated circuit of claim 1 comprising memory cells having a switch device.
15. The integrated circuit of claim 14 comprising memory cell switch devices having a permanently modifiable threshold voltage.
16. The integrated circuit of claim 14 comprising memory cells including a capacitor to store memory state.
17. The integrated circuit of claim 14 comprising memory cells including a ferro-electric material.
18. The integrated circuit of claim 14 comprising segment switch devices which are substantially identical in structure to the memory cell switch devices.
19. The integrated circuit of claim 14 comprising segment switch devices which are substantially different in structure than the memory cell switch devices.
20. The integrated circuit of claim 14 comprising memory cell switch devices which include a charge storage dielectric.
21. The integrated circuit of claim 20 comprising SONOS memory cell switch devices.
22. A monolithic integrated circuit comprising: a three-dimensional memory array having at least two memory planes stacked one above the other and further having a respective plurality of word lines on each of at least one layer of the memory array, having a respective plurality of bit line segments on each of at least one layer of the memory array, each memory plane comprising a vertically adjacent word line layer and segmented bit line layer, each memory plane comprising a plurality of memory segments, the three-dimensional array comprising a plurality of sub-arrays; a plurality of global bit line circuits each shared by a respective pair of adjacent sub-arrays, but disposed substantially beneath only one of the pair of adjacent sub-arrays; and a respective plurality of global bit lines on each of at least a first global bit line layer; wherein each memory segment comprises a bit line segment and a segment switch device for coupling the bit line segment to an associated global bit line; and wherein each global bit line is coupled to a respective segment switch device disposed within each respective memory plane.
23. The integrated circuit of claim 22 further comprising a plurality of shared vertical connections in the memory array, each coupling at least two memory segments to an associated global bit line.
24. The integrated circuit of claim 22 further comprising a plurality of shared vertical connections in the memory array, each coupling at least one memory segment on each of at least two respective memory planes to an associated global bit line.
25. The integrated circuit of claim 22 comprising EEPROM memory cells.
26. The integrated circuit of claim 22 comprising more than one type of memory cells within the three-dimensional memory array.
27. The integrated circuit of claim 22 further comprising: a respective plurality of global bias lines on at least a first global bias line layer; wherein each memory segment comprises a respective bias line segment and a respective bias switch device for coupling the respective bias line segment to an associated global bias line.
28. The integrated circuit of claim 22 comprising passive element memory cells.
29. The integrated circuit of claim 28 comprising anti-fuse memory cells.
30. The integrated circuit of claim 22 wherein the global bit lines run generally parallel to the bit line segments.
31. The integrated circuit of claim 30 comprising global bit lines having a resistance per unit length which is a least a factor of 5 lower than that of a bit line segment.
32. The integrated circuit of claim 30 comprising global bit lines having a capacitance per unit length which is a least a factor of 5 lower than that of a bit line segment.
33. The integrated circuit of claim 22 wherein respective pairs of adjacent memory segments are associated with a single respective bit line segment disposed therebetween, having a respective segment switch device for coupling the respective bit line segment to an associated global bit line.
34. The integrated circuit of claim 33 further comprising: a respective plurality of global bias lines on at least a first global bias line layer; and wherein respective pairs of adjacent memory segments are associated with a respective bias line segment therebetween, having a respective bias switch device for coupling the respective bias line segment to an associated global bias line.
35. The integrated circuit of claim 34 wherein: adjacent memory segments associated with the same bit line segment are associated with different global bias lines.
36. The integrated circuit of claim 22 comprising memory cells having a switch device.
37. The integrated circuit of claim 36 comprising memory cell switch devices having a permanently modifiable threshold voltage.
38. The integrated circuit of claim 36 comprising memory cells including a capacitor to store memory state.
39. The integrated circuit of claim 36 comprising memory cells including a ferro-electric material.
40. The integrated circuit of claim 36 comprising segment switch devices which are substantially identical in structure to the memory cell switch devices.
41. The integrated circuit of claim 36 comprising memory cell switch devices which include a charge storage dielectric.
42. The integrated circuit of claim 41 comprising SONOS memory cell switch devices.
43. The integrated circuit of claim 36 comprising segment switch devices which are substantially different in structure than the memory cell switch devices.
44. The integrated circuit of claim 43 comprising SONOS memory cell devices.
45. The integrated circuit of claim 44 comprising segment switch devices which contain no nitride but are otherwise substantially identical to the memory cell switch devices.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
June 18, 2007
February 25, 2014
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