The present invention provides a double-sided electrode package of a structure excellent in the reliability of connection and moisture resistance to another package, which is capable of being manufactured simply and at low cost. The present invention also provides a double-sided electrode package of a structure capable of forming inner wirings (electrode pads) in arbitrary layouts according to the number of pins of a semiconductor chip and the size thereof, which package is capable of being manufactured simply and at low cost. A copper foil is attached onto a core material formed with electrode pads, wirings, through electrodes, lands and a solder resist. The copper foil is wet-etched in several stages to form surface side terminals which stand on the wirings approximately vertically and each of which includes a plurality of protrusions (convex portions continuous in the circumferential direction) formed at their side faces over the full circumference along the circumferential direction. The peripheries of the surface side terminals are sealed with a sealing resin, and the end faces of the surface side terminals are exposed from a sealing resin layer, whereby redistribution wiring is performed at the surface of the sealing resin layer.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device comprising: a package substrate having electrode pads formed on a first surface thereof for being respectively electrically connected to electrodes of a semiconductor chip, and having external connecting pads formed on a second surface thereof and being electrically connected to the electrode pads; said semiconductor chip placed on the first surface of the package substrate and having the electrodes thereof respectively electrically connected to the electrode pads of the package substrate; post-like surface side terminals each having a plurality of protrusions formed around a side face thereof, each end portion of each said post-like surface side terminal being of a diameter that gradually increases towards an end of the terminal corresponding to the end portion, one end of each said surface side terminal being electrically connected to the electrode pads of the package substrate, each said post-like surface side terminal being of a height that is between twice and three times of a thickness of said semiconductor chip; and a sealing resin layer sealing the semiconductor chip and surrounding the surface side terminals from the side faces thereof, such that the other end of each surface side terminal is exposed from a surface of the sealing resin layer.
2. The semiconductor device according to claim 1 , wherein the surface side terminals are vertical to the first surface of the package substrate.
3. The semiconductor device according to claim 1 , wherein the surface side terminals are cylindrical or conical.
4. The semiconductor device according to claim 1 , wherein the surface side terminals are formed by etching a metal film laminated over the package substrate plural times each time removing a portion of the metal film from a top thereof.
5. The semiconductor device according to claim 1 , wherein the protrusions of the surface side terminals are formed by side etching the metal film during the etching of the metal film.
6. The semiconductor device according to claim 1 , further including: redistribution wiring pads formed on the surface of the sealing resin layer, and connecting wirings formed on the surface of the sealing resin layer and electrically connecting the other ends of the surface side terminals and the redistribution wiring pads.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
May 19, 2008
February 25, 2014
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