A memory device, system and method for allowing an early read operation after one or more write operations is provided according to an embodiment of the present invention. The memory device comprises an interface for providing a first write address, a first write data, and a read address. A memory core is coupled to the interface and includes a first memory section having a first data path and a first address path and a second memory section having a second data path and a second address path. In an embodiment of the present invention, the first data and first address path is independent of the second data and second address path. The first write data is provided on the first data path responsive to the first write address being provided on the first address path while a read data is provided on the second data path responsive to the read address being provided on the second address path.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A memory controller to control operation in a memory device having bank groups, the memory controller comprising: an interface to output commands to the memory device, the commands including at least three commands comprising a write command to a bank of a first bank group, a second command, and a read command to a bank of a second bank group, the commands ordered in the manner stated prior to being output; and logic to selectively reorder output of the commands, such that the interface is to output the read command prior to the second command.
2. The memory controller of claim 1 , wherein the memory controller is to transmit each of the commands to the memory device over an interconnect in an associated time slot, and wherein the logic to selectively reorder the output of the commands is to adjust order in which commands are transmitted to the memory device so as to advance the read command to an earlier time slot dependent on a condition where the read command is directed to a different bank group than the write command.
3. The memory controller of claim 1 , wherein the memory controller is to transmit at least one address bit that identifies bank group to the memory device for each of the write command and the read command.
4. The memory controller of claim 1 , wherein: the memory controller is to exchange data with the memory device over two external interconnects; and the memory controller is to generate a command to the memory device to couple a first of the two external interconnects to a selective one of the first bank group and the second bank group.
5. The memory controller of claim 1 , embodied as a dynamic random access memory (“DRAM”) controller, wherein the memory controller is operable to output a row activation command in association with each of the write command and the read command.
6. The memory controller of claim 1 , embodied as a dynamic random access memory (“DRAM”) controller, wherein the memory controller is operable to output a precharge command in association with the write command and wherein output of the precharge command does not affect spacing between output of a read command and output of a write command by the memory controller.
7. The memory controller of claim 1 , wherein the logic is to maintain a queue of commands respective to each bank group and to cause the memory controller to output a read command to a bank in the first bank group when a write command is pending to a bank in the second bank group, and to output a write command to a bank in the first bank group when a read command is pending to a bank in the second bank group.
8. The memory controller of claim 1 , wherein the logic is to maintain at least one queue of commands including write commands, and is to check the at least one queue to ensure that a read command will not attempt to perform a read operation at an address which has a pending write operation.
9. A memory controller to control operation in a memory device having bank groups, the memory controller comprising: an interface to output commands to the memory device, the commands including at least three commands comprising a write command directed to a bank in a first bank group, a second command, and a read command, the commands ordered in the manner stated and corresponding to respective time slots; and logic to selectively reorder time slots associated with at least two of the commands dependent on the read command being directed to a bank in a bank group other than the first bank group.
10. The memory controller of claim 9 , wherein the logic to selectively reorder is to adjust order in which commands are transmitted to the memory device so as to advance the read command to an earlier time slot dependent on the read command being directed to a bank in a bank group other than the first bank group.
11. The memory controller of claim 9 , wherein the memory controller is to transmit at least one address bit that identifies bank group to the memory device for each of the write command and the read command.
12. The memory controller of claim 10 , wherein: the memory controller is to exchange data with the memory device over two external interconnects; and the memory controller is to generate a command to the memory device to couple a first of the two external interconnects to a selective one of the first bank group and the bank group other than the first bank group.
13. The memory controller of claim 9 , embodied as a dynamic random access memory (“DRAM”) controller, wherein the memory controller is operable to output a precharge command in association with the write command and wherein output of the precharge command does not affect spacing between output of a read command and output of a write command by the memory controller.
14. The memory controller of claim 9 , wherein the logic is to maintain at least one queue of commands including write commands, and is to check the at least one queue to ensure that a read command will not attempt to perform a read operation at an address which has a pending write operation.
15. The memory controller of claim 9 , wherein: the memory controller is to exchange data with the memory device over two external interconnects of equal bandwidth; and the memory controller is operable to exchange data with the memory device using both of the two external interconnects in lockstep; and the memory controller is also to exchange data with the memory device using one of the two external interconnects for half-size independent access.
16. The memory controller of claim 15 , wherein the memory controller is to generate a command to the memory device to selectively couple one of the two external interconnects to a bank group.
17. The memory controller of claim 9 , wherein the interface is operable to also output to the memory device in association with the write command write data and mask data, wherein the mask data corresponds to at least one portion of write data that is not to be written to memory.
18. A method of controlling operation in a memory device having bank groups, the memory controller comprising: outputting at least three commands to the memory device, including a write command to a bank of a first bank group, a second command, and a read command to a bank of a second bank group, the commands ordered in the manner stated; and before the commands are output, reordering the commands, such that the read command is output prior to the second command, dependent on the read command being directed to a bank in a bank group other than the first bank group.
19. A memory controller to control operation in a memory device having bank groups, the memory controller comprising: an interface to output commands to the memory device, the commands including at least a write command and a read command; and logic to selectively reorder the read command when the write command is directed to a bank of a first bank group and the read command is directed to a bank of a second bank group, wherein the read command is output following output of the write command via the interface.
20. A memory controller to control operation in a memory device having bank groups, the memory controller comprising: an interface to output commands to the memory device, the commands including at least three commands comprising a write command to a bank of a first bank group, a second command, and a read command to a bank of a second bank group, the commands received by the memory controller in the stated order; and logic to selectively reorder the commands to be output such that the write command is directed to a bank of a first bank group and the read command is directed to a bank of a second bank group, wherein the read command is output to the memory device following output of the write command via the interface.
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December 12, 2012
March 4, 2014
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