An electronic device can include a nonvolatile memory cell that includes a capacitor, a tunnel structure, a state transistor, and an access transistor. In an embodiment, the capacitor and tunnel structure can include upper electrodes, wherein the upper electrode of the capacitor has a first conductivity type, and the upper electrode of the tunnel structure includes at least a portion that has a second conductivity type opposite the first conductivity type. In another embodiment, a process of forming the nonvolatile memory is performed using a single poly process. In a further embodiment, charge carriers can tunnel through a gate dielectric layer of the state transistor during programming and tunnel through a tunnel dielectric of the tunnel transistor during erasing.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An electronic device including a nonvolatile memory cell comprising: a capacitor having a first electrode and a second electrode, wherein a control gate terminal is coupled to the first electrode, and the second electrode has a first conductivity type; a tunnel structure having a first electrode and a second electrode, wherein an erase terminal is coupled to the first electrode, and at least a portion of the second electrode has a second conductivity type opposite the first conductivity type; a state transistor including a source region, a drain region, and a gate electrode, wherein a floating gate electrode for the nonvolatile memory cell includes the gate electrode, the second electrode of the capacitor, and the second electrode of the tunnel structure; an access transistor including a source region, a drain region, and a gate electrode, wherein the source region of the access transistor is coupled to the drain region of the state transistor; and a field isolation region, wherein the first electrode of the capacitor includes a first n-well region, wherein the first electrode of the tunnel structure includes a second n-well region, wherein the source and drain regions of the state and access transistors are disposed within a first p-type region, wherein portions of the field isolation region are disposed between the first n-well region, the second n-well region, and the first p-type region, and wherein the first n-well region, the second n-well region, and the first p-type region are electrically isolated from one another.
2. The electronic device of claim 1 , wherein the second electrode of the capacitor, the second electrode of the tunnel structure, the gate electrode of the state transistor, and the gate electrode of the access transistor are formed from a same layer comprising polycrystalline silicon or amorphous silicon.
3. The electronic device of claim 1 , further comprising a metal-containing member disposed over and substantially coterminous with the floating gate.
4. The electronic device of claim 1 , wherein the capacitor includes a p-channel transistor structure, the state transistor is a first n-channel transistor, and the access transistor is a second n-channel transistor.
5. The electronic device of claim 4 , wherein substantially all of the second electrode of the tunnel structure is n-type doped.
6. The electronic device of claim 5 , wherein the first electrode of the tunnel structure includes an n-well region and a p-type region that is disposed within the n-well region and adjacent to the second electrode of the tunnel structure.
7. The electronic device of claim 6 , further comprising: an n-well contact region disposed within the n-well region and adjacent to the p-type region; and a metal-containing member that contacts the n-well contact region.
8. The electronic device of claim 5 , wherein the first electrode of the tunnel structure includes an n-well region that does not include a p-type region.
9. The electronic device of claim 1 , further comprising a second p-type doped region disposed below a particular portion of the field isolation region, wherein: the substrate includes a semiconductor material and a dopant at a dopant concentration; the second p-type doped region has a dopant concentration that is greater than the dopant concentration of the semiconductor material; and the particular portion of the field isolation region abuts the first and second n-well regions.
10. The electronic device of claim 9 , further comprising a p-type body contact region disposed within the first p-type region, wherein another particular portion of the field isolation region is disposed between the p-type body contact region and the state and access transistors.
11. The electronic device of claim 1 , wherein the floating gate electrode is at least part of a single conductive member that further includes the second electrode of the tunnel structure.
12. The electronic device of claim 11 , wherein the single conductive member further includes the second electrode of the capacitor.
13. The electronic device of claim 1 , wherein the gate electrode of the access transistor is part of a word line.
14. An electronic device including a nonvolatile memory cell comprising: a capacitor having a first electrode and a second electrode, wherein a control gate terminal is coupled to the first electrode, and the second electrode has a first conductivity type; a tunnel structure having a first electrode and a second electrode, wherein an erase terminal is coupled to the first electrode, and the least a portion of the second electrode has a second conductivity type opposite the first conductivity type; a state transistor including a source region, a drain region, and a gate electrode, wherein a floating gate electrode for the nonvolatile memory cell includes the gate electrode, the second electrode of the capacitor, and the second electrode of the tunnel structure; and an access transistor including a source region, a drain region, and a gate electrode, wherein the source region of the access transistor is coupled to the drain region of the state transistor, wherein the first electrode of the tunnel structure includes an n-well region, wherein the second electrode of the tunnel structure includes a p-type portion and an n-type portion, wherein the p-type portion is adjacent to a first side of the second electrode, and the n-type portion is adjacent to a second side of the second electrode that is opposite the first side, wherein a p-type region is disposed within the n-well region and adjacent to the first side of the second electrode, and wherein an n-type region is disposed within the n-well region, having a higher dopant concentration than the n-well region, and is adjacent to the second side of the second electrode.
15. An electronic device including a nonvolatile memory cell comprising: a capacitor having a first electrode and a second electrode, wherein a control gate terminal is coupled to the first electrode; a tunnel structure having a first electrode, a second electrode, and a tunnel dielectric layer, wherein an erase terminal is coupled to the first electrode; a state transistor including a source region coupled to a source terminal, a drain region, a gate dielectric layer, and a gate electrode, wherein a floating gate of the nonvolatile memory cell includes the gate electrode, the second electrode of the capacitor, and the second electrode of the tunnel structure; and an access transistor including a source region, a drain region coupled to a bit line terminal, and a gate electrode coupled to an access terminal, wherein the source region of the access transistor is coupled to the drain region of the state transistor; a program unit coupled to the control gate terminal, the erase terminal, the source terminal, the bit line terminal, and the access terminal, wherein the program unit is configured to program the nonvolatile memory cell by passing a first charge carrier through the gate electric layer of the state transistor; and an erase unit coupled to the control gate terminal, the erase terminal, the source terminal, the bit line terminal, and the access terminal, wherein the erase unit is configured to erase the nonvolatile memory cell by passing a second charge carrier through the tunnel dielectric layer of the tunnel structure.
16. The electronic device of claim 15 , wherein each of the capacitor and the tunnel structure comprises a p-type transistor structure.
17. The electronic device of claim 15 , wherein: the control gate terminal is electrically connected to the first electrode of the capacitor; the erase terminal is electrically connected to the first electrode of the tunnel structure; the source terminal is electrically connected to the source region of the state transistor; the bit line is electrically connected to the drain region of the access transistor; and the source region of the access transistor is connected to the drain region of the state transistor.
18. The electronic device of claim 15 , wherein the floating gate electrode is at least part of a single conductive member that further includes the second electrode of the tunnel structure.
19. The electronic device of claim 18 , wherein the single conductive member further includes the second electrode of the capacitor.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
March 1, 2013
March 11, 2014
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