Method for manufacturing semiconductor device having interlayer dielectric layers and a gate contact

1. A method for manufacturing a semiconductor device, comprising the steps of: providing a substrate for the semiconductor device, the substrate having an active area and a gate structure including a gate on the active area and being formed with a first interlayer dielectric layer over the substrate, wherein the first interlayer dielectric layer has a first opening penetrating through the first interlayer dielectric layer to expose a portion of a surface of the active area, and an upper surface of the first interlayer dielectric layer is substantially flush with an upper surface of the gate; filling the first opening with a first conductive material to form a first portion of a contact; forming a second interlayer dielectric layer over the first interlayer dielectric layer, the second interlayer dielectric layer having a second opening penetrating through the second interlayer dielectric layer to substantially expose an upper part of the first portion of the contact in the first opening; and filling the second opening with a second conductive material to form a second portion of the contact; wherein at least one second opening is formed to substantially expose an upper part of the first portion of the contact and at least a portion of an upper surface of at least one gate.

2. The method according to claim 1 , wherein the exposed surface of the active area is on one or more of a source region or a drain region in the semiconductor device.

3. The method according to claim 2 , wherein the gate structure further comprises a dielectric layer underlying the gate and a spacer for the gate.

4. The method according to claim 1 , wherein the gate is a dummy gate, and the gate structure further comprises a dielectric layer underlying the gate and a spacer for the gate, the method further comprising: implanting, after the formation of the gate structure having the dummy gate, so as to form a source region and a drain region in the active area; forming the first interlayer dielectric layer over the substrate and performing chemical mechanical polishing, so as to expose the top surface of the dummy gate; removing the dummy gate; and forming a gate dielectric layer and a metal gate such that an upper surface of the metal gate is substantially flush with an upper surface of the first interlayer dielectric layer.

5. The method according to claim 1 , wherein the gate is a metal gate or a poly-silicon gate, and the gate structure further comprises a dielectric layer underlying the gate and a spacer for the gate, and the method further comprising: implanting, after the formation of the gate structure, so as to form a source region and a drain region in the active area; forming the first interlayer dielectric layer on the substrate and performing chemical mechanical polishing such that an upper surface of the gate is substantially flush with an upper surface of the first interlayer dielectric layer.

6. The method according to claim 1 , wherein the step of filling the first opening with a first conductive material comprises: depositing the first conductive material on the substrate such that the first opening is filled with the first conductive material; and removing the first conductive material such that at least a portion of the first conductive material in the first opening remains.

7. The method according to claim 1 , wherein the transversal size of the second opening is larger than or equal to the transversal size of the corresponding first opening.

8. The method according to claim 1 , wherein the second conductive material is the same as or different from the first conductive material.

9. The method according to claim 1 , wherein the first and second conductive materials can be selected from: tungsten (W), gold (Au), silver (Ag), rhodium (Rh), iridium (Ir), and copper (Cu).