A semiconductor system includes a controller configured to output a clock enable signal, first to third command/address signals, a chip select signal, first and second entry commands and an exit command, and receive an output signal; and a semiconductor device configured to latch the first and second command/address signals and transfer the output signal in response to the chip select signal and the first entry command, latch the first and third command/address signals and transfer the output signal in response to the chip select signal and the second entry command, and transfer data generated by the first to third command/address signals as the output signal in response to the clock enable signal and the exit command signal.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor system comprising: a controller configured to output a clock enable signal, first to third command/address signals, a chip select signal, first and second entry commands and an exit command, and receive an output signal; and a semiconductor device configured to latch the first and second command/address signals and transfer the output signal in response to the chip select signal and the first entry command, latch the first and third command/address signals and transfer the output signal in response to the chip select signal and the second entry command, and transfer data generated by the first to third command/address signals as the output signal in response to the clock enable signal and the exit command signal.
2. The semiconductor system according to claim 1 , wherein the controller controls setup/hold times of the first to third command/address signals by receiving the output signal which is generated by latching the first to third command/address signals.
3. The semiconductor system according to claim 1 , wherein the semiconductor device latches the first and second command/address signals and transfers the output signal in response to the first entry command, and latches the first and third command/address signals and transfers the output signal in response to the second entry command, during a period in which the clock enable signal is disabled.
4. The semiconductor system according to claim 1 , wherein the semiconductor device comprises: a signal generation block configured to generate a strobe signal, first and second calibration signals and a control signal in response to an internal clock, the clock enable signal, the chip select signal, the first and second entry commands and the exit command; a latch block configured to latch the first command/address signal in response to the strobe signal and generate a first latched command/address signal; a selective latch block configured to latch the second or third command/address signal in response to the strobe signal and the first and second calibration signals and generate a selectively latched command/address signal; a read path circuit configured to receive the first to third command/address signals and generate the data; and a multiplexer configured to transfer the data or the first latched command/address signal and the selectively latched command/address signal as the output signal in response to the control signal.
5. The semiconductor system according to claim 4 , wherein the signal generation block comprises: a calibration signal generation unit configured to generate a calibration signal and the first and second calibration signals in response to the first and second entry commands and the exit command; a strobe signal generation unit configured to generate the strobe signal in response to the chip select signal, the internal clock and the calibration signal; and a control signal generation unit configured to generate the control signal in response to the first and second calibration signals and the clock enable signal.
6. The semiconductor system according to claim 5 , wherein the calibration signal generation unit generates the first calibration signal which is enabled in response to the first entry command and is disabled in response to the second entry command or the exit command.
7. The semiconductor system according to claim 5 , wherein the calibration signal generation unit generates the second calibration signal which is enabled in response to the second entry command and is disabled in response to the first entry command or the exit command.
8. The semiconductor system according to claim 5 , wherein the calibration signal generation unit generates the calibration signal which is enabled when the first or second calibration signal is enabled.
9. The semiconductor system according to claim 5 , wherein the calibration signal generation unit comprises: a first calibration signal generating section configured to generate the first calibration signal which is enabled in response to the first entry command and is disabled in response to the second entry command or the exit command; and a second calibration signal generating section configured to generate the second calibration signal which is enabled in response to the second entry command and is disabled in response to the first entry command or the exit command.
10. The semiconductor system according to claim 5 , wherein the strobe signal generation unit generates the strobe signal by buffering the internal clock during a period in which the calibration signal and the chip select signal are enabled.
11. The semiconductor system according to claim 5 , wherein the strobe signal generation unit comprises: a driving signal generating section configured to generate a pull-up driving signal and a pull-down driving signal in response to the chip select signal and the internal clock; a driving latch section configured to generate a drive signal in response to the pull-up driving signal and the pull-down driving signal; a delay buffer section configured to buffer the internal clock and generate a delayed internal clock during a period in which the calibration signal is enabled; and an output section configured to receive the drive signal and the delayed internal clock and generate the strobe signal.
12. The semiconductor system according to claim 11 , wherein the driving signal generating section comprises: a switching part configured to be turned on in response to the internal clock; a precharge part configured to precharge the pull-up driving signal and the pull-down driving signal in response to the internal clock; and a cross-coupled amplification part configured to generate the pull-up driving signal and the pull-down driving signal in response to the chip select signal.
13. The semiconductor system according to claim 5 , wherein the control signal generation unit generates the control signal which is enabled in response to the first or second entry command and is disabled in response to the clock enable signal.
14. The semiconductor system according to claim 5 , wherein the control signal generation unit comprises: a first pulse signal generating section configured to generate a first pulse signal in response to the first calibration signal; a second pulse signal generating section configured to generate a second pulse signal in response to the second calibration signal; a third pulse signal generating section configured to generate a third pulse signal in response to the clock enable signal; and an RS latch section configured to receive the first and second pulse signals as set signals and the third pulse signal as a reset signal and generate the control signal.
15. The semiconductor system according to claim 4 , wherein the selective latch block latches the second command/address signal in response to the strobe signal during a period in which the first calibration signal is enabled and transfers the selectively latched command/address signal, and latches the third command/address signal in response to the strobe signal during a period in which the second calibration signal is enabled and transfers the selectively latched command/address signal.
16. The semiconductor system according to claim 4 , wherein the selective latch block comprises: a first latch unit configured to latch the second command/address signal in response to the strobe signal and generate a second latched command/address signal; a second latch unit configured to latch the third command/address signal in response to the strobe signal and generate a third latched command/address signal; and a selective transfer unit configured to selectively transfer the second or third command/address signal as the selectively latched command/address signal in response to the first and second calibration signals.
17. A semiconductor device comprising: a signal generation block configured to generate a strobe signal, first and second calibration signals and a control signal in response to an internal clock, a clock enable signal, a chip select signal, first and second entry commands and an exit command; a latch block configured to latch a first command/address signal in response to the strobe signal and generate a first latched command/address signal; a selective latch block configured to latch a second or third command/address signal in response to the strobe signal and the first and second calibration signals and generate a selectively latched command/address signal; a read path circuit configured to receive the first to third command/address signals and generate data; and a multiplexer configured to transfer the data or the first latched command/address signal and the selectively latched command/address signal as an output signal in response to the control signal.
18. The semiconductor device according to claim 17 , wherein the first and second entry commands and the exit command are set by a mode register set, and wherein the semiconductor device further comprises: a controller configured to receive the output signal and control setup/hold times of the first to third command/address signals.
19. The semiconductor device according to claim 18 , wherein the signal generation block comprises: a calibration signal generation unit configured to generate a calibration signal and the first and second calibration signals in response to the first and second entry commands and the exit command; a strobe signal generation unit configured to generate the strobe signal in response to the chip select signal, the internal clock and the calibration signal; and a control signal generation unit configured to generate the controls signal in response to the first and second calibration signals and the clock enable signal.
20. The semiconductor device according to claim 19 , wherein the calibration signal generation unit generates the first calibration signal which is enabled in response to the first entry command and is disabled in response to the second entry command or the exit command.
21. The semiconductor device according to claim 19 , wherein the calibration signal generation unit generates the second calibration signal which is enabled in response to the second entry command and is disabled in response to the first entry command or the exit command.
22. The semiconductor device according to claim 19 , wherein the calibration signal generation unit generates the calibration signal which is enabled when the first or second calibration signal is enabled.
23. The semiconductor device according to claim 19 , wherein the calibration signal generation unit comprises: a first calibration signal generating section configured to generate the first calibration signal which is enabled in response to the first entry command and is disabled in response to the second entry command or the exit command; and a second calibration signal generating section configured to generate the second calibration signal which is enabled in response to the second entry command and is disabled in response to the first entry command or the exit command.
24. The semiconductor device according to claim 19 , wherein the strobe signal generation unit generates the strobe signal by buffering the internal clock during a period in which the calibration signal and the chip select signal are enabled.
25. The semiconductor device according to claim 19 , wherein the strobe signal generation unit comprises: a driving signal generating section configured to generate a pull-up driving signal and a pull-down driving signal in response to the chip select signal and the internal clock; a driving latch section configured to generate a drive signal in response to the pull-up driving signal and the pull-down driving signal; a delay buffer section configured to buffer the internal clock and generate a delayed internal clock during a period in which the calibration signal is enabled; and an output section configured to receive the drive signal and the delayed internal clock and generate the strobe signal.
26. The semiconductor device according to claim 25 , wherein the driving signal generating section comprises: a switching part configured to be turned on in response to the internal clock; a precharge part configured to precharge the pull-up driving signal and the pull-down driving signal in response to the internal clock; and a cross-coupled amplification part configured to generate the pull-up driving signal and the pull-down driving signal in response to the chip select signal.
27. The semiconductor device according to claim 19 , wherein the control signal generation unit generates the control signal which is enabled in response to the first or second entry command and is disabled in response to the clock enable signal.
28. The semiconductor device according to claim 19 , wherein the control signal generation unit comprises: a first pulse signal generating section configured to generate a first pulse signal in response to the first calibration signal; a second pulse signal generating section configured to generate a second pulse signal in response to the second calibration signal; a third pulse signal generating section configured to generate a third pulse signal in response to the clock enable signal; and an RS latch section configured to receive the first and second pulse signals as set signals and the third pulse signal as a reset signal and generate the control signal.
29. The semiconductor device according to claim 17 , wherein the selective latch block latches the second command/address signal in response to the strobe signal during a period in which the first calibration signal is enabled and transfers the selectively latched command/address signal, and latches the third command/address signal in response to the strobe signal during a period in which the second calibration signal is enabled and transfers the selectively latched command/address signal.
30. The semiconductor device according to claim 17 , wherein the selective latch block comprises: a first latch unit configured to latch the second command/address signal in response to the strobe signal and generate a second latched command/address signal; a second latch unit configured to latch the third command/address signal in response to the strobe signal and generate a third latched command/address signal; and a selective transfer unit configured to selectively transfer the second or third command/address signal as the selectively latched command/address signal in response to the first and second calibration signals.
31. A method for controlling setup/hold times of command/address signal, comprising: applying first to third command/address signals, a first entry command, a clock enable signal and a chip select signal to a semiconductor device from a controller; generating first and second latched command/address signals which are generated by latching the first and second command/address signals during a period in which the clock enable signal is disabled and the chip select signal is enabled, and transmitting the first and second latched command/address signals to the controller from the semiconductor device; applying the first to third command/address signals, a second entry command, the clock enable signal and the chip select signal to the semiconductor device from the controller; generating first and third latched command/address signals which are generated by latching the first and third command/address signals during a period in which the clock enable signal is disabled and the chip select signal is enabled, and transmitting the first and third latched command/address signals to the controller from the semiconductor device; and controlling setup/hold times of the first to third latched command/address signals by the controller.
32. The method according to claim 31 , wherein controlling the setup/hold times of the first to third latched command/address signals by the controller comprises: applying the first to third command/address signals, the exit command and the clock enable signal to the semiconductor device from the controller; and transmitting data generated by the first to third command/address signals during a period in which the clock enable signal is enabled, to the controller from the semiconductor device.
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August 21, 2012
March 18, 2014
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