A semiconductor device includes a semiconductor substrate in which a diode region and an IGBT region are formed, wherein a lower surface side of the semiconductor substrate comprises a low impurity region provided between a second conductivity type cathode region of the diode region and a first conductivity type collector region of the IGBT region. The low impurity region includes at least one of a first conductivity type first low impurity region which has a lower density of first conductivity type impurities than that in the collector region and a second conductivity type second low impurity region which has a lower density of second conductivity type impurities than that in the cathode region.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device comprising a semiconductor substrate in which a diode region and an IGBT region are formed, wherein the diode region comprises: a first conductivity type anode region exposed at an upper surface of the semiconductor substrate, a second conductivity type diode drift region formed on a lower surface side of the anode region, and a second conductivity type cathode region, which has a higher density of second conductivity type impurities than in the diode drift region, formed on a lower surface side of the diode drift region, the diode drift region comprises an upper drift layer and a lower drift layer which has a higher density of second conductivity type impurities than the upper drift layer, the IGBT region comprises: a second conductivity type emitter region exposed at the upper surface of the semiconductor substrate, a first conductivity type body region formed at a side and a lower surface side of the emitter region and in contact with an emitter electrode, a second conductivity type IGBT drift region formed on a lower surface side of the body region, a first conductivity type collector region formed on a lower surface side of the IGBT drift region, and a gate electrode facing a range of the body region via an insulating film, wherein the range of the body region separates the emitter region from the IGBT drift region, the IGBT drift region comprises an IGBT drift layer and a buffer layer which has a higher density of second conductivity type impurities than the IGBT drift layer, a low impurity region is formed between the cathode region and the collector region at a lower surface of the semiconductor substrate, the low impurity region comprises at least one of a first conductivity type first low impurity region which has a lower density of first conductivity impurities than that in the collector region and a second conductivity type second low impurity region which has a lower density of second conductivity impurities than that in the cathode region, and the lower drift layer and the buffer layer are continuous with each other on an upper side of the low impurity region.
2. The semiconductor device according to claim 1 , further comprising an electrode in contact with the lower surface of the semiconductor substrate, wherein the cathode region, the collector region and the low impurity region are exposed at the lower surface of the semiconductor substrate, and a contact resistance of the low impurity region and the electrode is higher than both of a contact resistance of the cathode region and the electrode and a contact resistance of the collector region and the electrode.
3. The semiconductor device according to claim 1 , wherein a boundary between the cathode region and the low impurity region is located on a diode region side from a position under the body region of the IGBT region in a plan view of the semiconductor device.
4. The semiconductor device according to claim 1 , wherein a lifetime control region is formed in the diode drift region, a lifetime of a carrier in the lifetime control region is shorter than that in the diode drift region outside the lifetime control region, and an IGBT region side end of the lifetime control region is located above the low impurity region in a plan view of the semiconductor device.
5. The semiconductor device according to claim 1 , wherein a first conductivity type separation region is formed in a range between the diode region and the IGBT region and extending from the upper surface of the semiconductor substrate to a position deeper than both of a lower end of the anode region and a lower end of the body region, and an IGBT region side end of a lifetime control region is located under the separation region in a plan view of the semiconductor device.
6. A method for manufacturing the semiconductor device according to claim 1 , the method comprising: a masking step of disposing a mask on one of a lower surface side of a diode forming region and a lower surface side of an IGBT forming region of a semiconductor wafer; an ion doping step of doping impurity ions from a lower surface side of the mask to a lower surface of the semiconductor wafer and forming an ion doping region; and an annealing step of annealing the ion doping region; wherein the ion doping step comprises: a first ion doping step of doping the impurity ions in a first direction from a region on which the mask has been formed in the masking step to a region on which the mask was not formed, the first direction making an acute angle with the lower surface of the semiconductor wafer, and a second ion doping step of doping the impurity ions in a second direction which intersects with the first direction.
7. A method for manufacturing the semiconductor device according to claim 1 , the method comprising: a masking step of disposing a mask on one of a lower surface side of a diode forming region and a lower surface side of an IGBT forming region of a semiconductor wafer, an ion doping step of doping impurity ions from a lower surface side of the mask to a lower surface of the semiconductor wafer and forming an ion doping region, and a laser annealing step of performing laser annealing of the ion doping region with the mask being disposed.
8. The method according to claim 6 for manufacturing the semiconductor device, wherein the mask is fixed in the masking step with the semiconductor wafer via a bond layer which is in contact with the lower surface of the semiconductor wafer.
9. A method for manufacturing the semiconductor device according to claim 1 , the method comprising: a masking step of disposing a mask on one of a lower surface side of a diode forming region and a lower surface side of an IGBT forming region of a semiconductor wafer, an ion doping step of doping impurity ions from a lower surface side of the mask to a lower surface of the semiconductor wafer and forming the first conductivity type collector region and the second conductivity type cathode region, which are adjacent to each other, and a laser annealing step of performing laser annealing of a boundary between the collector region and the cathode region in the lower surface of the semiconductor wafer.
10. The method according to claim 6 for manufacturing the semiconductor device wherein the mask is disposed on the lower surface side of the IGBT forming region of the semiconductor wafer in the masking step, and the method further comprises a crystal defect forming step of irradiating charged particles from the lower surface side of the mask to the lower surface of the semiconductor wafer and forming the crystal defect in the diode forming region of the semiconductor wafer.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
September 11, 2012
April 1, 2014
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