In a semiconductor storage apparatus, an internal address generation unit generates, when receiving successive first and second external addresses, from the second external address an internal address for selecting any of the memory cells connected to bit lines and word lines except the bit line and word line connected to a memory cell to be selected according to the first external address. When receiving the successive external addresses, a memory cell connected to the same bit line and word line is not continuously selected, and erroneous readout due to rewriting of a value of the memory cell in a non-selected state is suppressed.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor storage apparatus comprising: a memory cell array configured to include a plurality of memory cells each connected to a bit line and a word line; and an internal address generation unit configured to generate, when receiving successive first and second external addresses, from the second external address an internal address for selecting any of the memory cells connected to bit lines and word lines except the bit line and word line connected to a memory cell to be selected according to the first external address.
2. The semiconductor storage apparatus according to claim 1 , wherein: the memory cell array includes a plurality of blocks in which reading or writing of data is separately performed; and the internal address generation unit generates from the second external address an internal address for selecting a memory cell included in a block different from that including a memory cell to be selected according to the first external address.
3. The semiconductor storage apparatus according to claim 1 , wherein the internal address generation unit generates, when a specific bit of an external address to be received is invalid, from the second external address an internal address for selecting any of the memory cells connected to bit lines and word lines except the bit line and word line connected to a memory cell to be selected according to the first external address.
4. The semiconductor storage apparatus according to claim 3 , wherein among the received external addresses, at least one bit except for the specific bit is a fixed value of 0 or 1, and the internal address generation unit makes a part of the internal address invalid.
5. A semiconductor integrated circuit comprising: a plurality of external terminals configured to receive an external address; and a semiconductor storage apparatus including: a memory cell array configured to include a plurality of memory cells each connected to a bit line and a word line; and an internal address generation unit configured to generate, when receiving successive first and second external addresses, from the second external address an internal address for selecting any of the memory cells connected to bit lines and word lines except the bit line and word line connected to a memory cell to be selected according to the first external address.
6. The semiconductor integrated circuit according to claim 5 , wherein: the semiconductor storage apparatus is provided in plurality; the internal address generation unit of each semiconductor storage apparatus generates, when a specific bit of the received external address is invalid, from the second external address an internal address for selecting any of the memory cells connected to bit lines and word lines except the bit line and word line connected to a memory cell to be selected according to the first external address; and out of the plurality of external terminals, an external terminal to input the specific bit is provided in each of the semiconductor storage apparatus.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
September 11, 2012
April 1, 2014
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