A semiconductor device includes a semiconductor substrate having an active layer in which an element region and a contact region are formed, a support substrate supporting the active layer, and a buried insulation layer interposed between the active layer and the support substrate. A transistor element is formed in the element region, the transistor element having a transistor buried impurity layer formed within the active layer. The semiconductor device further includes a substrate contact having a contact buried impurity layer formed within the contact region and a through contact extending from the surface of the active layer to the support substrate through the contact buried impurity and the buried insulation layer, the contact buried impurity layer being in the same layer as the transistor buried impurity layer.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device, comprising: a semiconductor substrate including an active layer having a first conductive type in which an element region and a contact region are formed, a support substrate having a second conductive type and supporting the active layer, and a buried insulation layer interposed between the active layer and the support substrate to electrically insulate the active layer and the support substrate; a transistor element formed in the element region, the transistor element including a transistor buried impurity layer formed within the active layer and being spaced apart from a surface of the active layer; and a substrate contact including a contact buried impurity layer formed within the contact region and a through contact extending from the surface of the active layer to the support substrate through the contact buried impurity and the buried insulation layer, the contact buried impurity layer corresponding to the same layer as the transistor buried impurity layer.
2. The semiconductor device of claim 1 , further comprising: a field insulation film formed on the surface of the active layer, the field insulation film including an opening for exposing a portion of the contact region, wherein a width of the contact buried impurity layer along the surface of the active layer is greater than a width of the opening of the field insulation film.
3. The semiconductor device of claim 1 , wherein the transistor element further includes a transistor exposing impurity layer formed on the transistor buried impurity layer, and the transistor exposing impurity layer is formed a portion of the surface of the active layer, and wherein the substrate contact further includes a contact exposing impurity layer formed as the same layer as the transistor exposing impurity layer and the contact exposing impurity layer is disposed to be in contact with the through contact.
4. The semiconductor device of claim 1 , wherein the transistor element includes a CMOS transistor having first and second transistors, wherein the first transistor includes a CMOS buried layer as the transistor buried impurity layer, and the first transistor has the same conductivity type as the first conductivity type of the active layer, the second transistor includes a CMOS isolation layer as the transistor buried impurity layer, and the second transistor has an opposite conductivity type to the first conductivity type of the active layer, and the contact buried impurity layer is formed as the same layer as at least one of the CMOS buried layer and the CMOS isolation layer.
5. The semiconductor device of claim 4 , wherein the transistor element further includes a transistor exposing impurity layer formed on the transistor buried impurity layer, and the transistor exposing impurity layer forms a portion of the surface of the active layer, and the substrate contact further includes a contact exposing impurity layer, and the contact exposing impurity layer is formed as the same layer as the transistor exposing impurity layer and is disposed to be in contact with the through contact, wherein the first transistor includes a first well layer as the transistor exposing impurity layer having the same conductivity type as the first conductivity type of the active layer and disposed to be in contact with the CMOS buried layer, and the transistor exposing impurity layer includes a first source layer and a first drain layer and as has an opposite conductivity type to the first conductivity type of the active layer, and the first source layer and the first drain layer are formed to be spaced apart from each other in a surface layer portion of the first well layer, wherein the second transistor includes a second well layer as the transistor exposing impurity layer having the opposite conductivity type to the first conductivity type of the active layer and is disposed to be in contact with the CMOS isolation layer, and the transistor exposing impurity layer includes a second source layer and a second drain layer and has the same conductivity type as the first conductivity type of the active layer, and the second source layer and the second drain layer are formed to be spaced apart from each other in a surface layer portion of the second well layer, and wherein the contact exposing impurity layer is formed as the same layer as at least one of the first well layer, the second well layer, the first source layer, the first drain layer, the second source layer, and the second drain layer.
6. The semiconductor device of claim 1 , wherein the transistor element includes a bipolar transistor, the bipolar transistor includes a collector layer as the transistor buried impurity layer having the same conductivity type as the first conductivity type of the active layer, and the contact buried impurity layer is formed as the same layer as the collector layer.
7. The semiconductor device of claim 6 , wherein the transistor element further includes a transistor exposing impurity layer formed on the transistor buried impurity layer, and the transistor exposing impurity layer forms a portion of the surface of the active layer, and the substrate contact further includes a contact exposing impurity layer, and the contact exposing impurity layer is formed as the same layer as the transistor exposing impurity layer and disposed to be in contact with the through contact, wherein the bipolar transistor includes: a base layer as the transistor exposing impurity layer having the opposite conductivity type to the first conductivity type of the active layer and formed to be spaced apart from the collector layer, and an emitter layer as the transistor exposing impurity layer having the same conductivity type as the first conductivity type of the active layer and formed in a surface layer portion of the base layer, and wherein the contact exposing impurity layer is formed as the same layer as at least one of the base layer and the emitter layer.
8. The semiconductor device of claim 7 , wherein the bipolar transistor further includes a sinker layer as the transistor exposing impurity layer, and the sinker layer has the same conductivity type to the first conductivity type of the active layer and extends from the surface of the active layer to reach the collector layer, and wherein the contact exposing impurity layer includes a layer formed as the same layer as the sinker layer.
9. The semiconductor device of claim 1 , wherein the element region is demarcated by an element isolating portion, and the element isolating portion is formed to have an annular shape surrounding the transistor element and insulates the element region from other portions of the active layer.
10. The semiconductor device of claim 9 , wherein the element isolating portion includes a first annular deep trench extending from the surface of the active layer to reach the buried insulation layer, a first insulation film formed on an inner wall of the first deep trench, and a first semiconductor layer charged in the first deep trench.
11. The semiconductor device of claim 1 , wherein the contact region includes an internal contact region installed within the element region.
12. The semiconductor device of claim 1 , wherein the contact region includes an external contact region installed outside the element region.
13. The semiconductor device of claim 1 , further comprising: an interlayer insulation film formed on the semiconductor substrate; and an electrode pad formed on the interlayer insulation film, wherein the substrate contact is installed under the electrode pad.
14. The semiconductor device of claim 1 , wherein the contact region is demarcated by a contact isolating portion, and the contact isolating portion is formed to have an annular shape surrounding the substrate contact and extends from the surface of the active layer to reach the buried insulation layer.
15. The semiconductor device of claim 14 , wherein the contact isolating portion includes a second annular deep trench extending from the surface of the active layer to reach the buried insulation layer, a second insulation film formed on an inner wall of the second deep trench, and a second semiconductor layer charged in the second deep trench.
16. The semiconductor device of claim 1 , wherein the first and second conductivity types are the same conductivity type.
17. The semiconductor device of claim 1 , wherein the first and second conductivity types are different conductivity types.
18. The semiconductor device of claim 1 , wherein the substrate contact includes a lower implanted layer formed at a connection portion with the through contact in the support substrate.
19. The semiconductor device of claim 18 , wherein the substrate contact includes a first substrate contact with the lower implanted layer having the same conductivity type as the second conductivity type of the support substrate.
20. The semiconductor device of claim 1 , wherein the substrate contact includes a second substrate contact with a lower implanted layer having an opposite conductivity type to the second conductivity type of the support substrate.
21. The semiconductor device of claim 1 , wherein the semiconductor substrate includes an SOI substrate in which the active layer and the support substrate are made of silicon and the buried insulation layer is made of a silicon oxide.
22. The semiconductor device of claim 1 , wherein the through contact is made of polysilicon.
23. A method for fabricating a semiconductor device, comprising: preparing a semiconductor substrate including an active layer with a first conductive type in which an element region and a contact region are formed, a support substrate with a second conductive type supporting the active layer, and a buried insulation layer interposed between the active layer and the support substrate to electrically insulate the active layer and the support substrate; selectively implanting an impurity into the element region and the contact region from a surface of the active layer to simultaneously form a first impurity layer exposed from a surface of the element region and a second impurity layer exposed from a surface of the contact region; epitaxially growing the active layer to raise the height of the surface of the active layer with respect to the buried insulation layer to form the first impurity layer as a transistor buried impurity layer spaced apart from the raised surface, and to simultaneously form the second impurity layer as a contact buried impurity layer spaced apart from the raised surface; forming a transistor element having the transistor buried impurity layer in the element region; and forming a trench extending from the surface of the active layer to the support substrate through the contact buried impurity and the buried insulation layer and embedding a through contact in contact with both of the active layer and the support substrate within the trench to form a substrate contact having the contact buried impurity layer and the through contact in the contact region.
24. The method of claim 23 , further comprising: forming a field insulation film on the surface of the active layer once the substrate contact is formed; and forming an opening having a width smaller than a width of the contact buried impurity layer along the surface of the active layer in the field insulation film by removing a portion of the field insulation film in the contact region.
25. The method of claim 23 , wherein said forming a transistor element further comprises forming a transistor exposing impurity layer to form a first portion of the surface of the active layer on the transistor buried impurity layer by selectively implanting a first impurity into the element region from the surface of the active layer once the transistor buried impurity layer is formed, and wherein said forming a substrate contact further comprises forming a contact exposing impurity layer to form a second portion of the surface of the active layer on the contact buried impurity layer by selectively implanting a second impurity into the contact region simultaneously when implanting the first impurity into the element region.
26. The method of claim 23 , wherein said forming a transistor buried impurity layer comprises: forming a CMOS buried layer as the transistor buried impurity layer having the same conductivity type as the first conductivity type of the active layer, and forming a CMOS isolation layer having an opposite conductivity type to the first conductivity type of the active layer, and wherein said forming a transistor element comprises forming a CMOS transistor including a first transistor having the CMOS buried layer and a second transistor having the CMOS isolation layer, and said forming a contact buried impurity layer is simultaneously performed with at least one of said forming a CMOS buried layer and said forming a CMOS isolation layer.
27. The method of claim 26 , wherein said forming a transistor element further comprises forming a transistor exposing impurity layer to form a first portion of the surface of the active layer on the transistor buried impurity layer by selectively implanting a first impurity into the element region from the surface of the active layer once the transistor buried impurity layer is formed, wherein said forming a substrate contact further comprises forming a contact exposing impurity layer to form a second portion of the surface of the active layer on the contact buried impurity layer by selectively implanting a second impurity into the contact region simultaneously when implanting the first impurity into the element region, wherein said forming a transistor exposing impurity layer comprises: forming a first well layer as the transistor exposing impurity layer having the same conductivity type as the first conductivity type of the active layer to be in contact with the CMOS buried layer; forming a first source layer and a first drain layer having an opposite conductivity type to that of the active layer to be spaced apart from each other in a surface layer portion of the first well layer; forming a second well layer having an opposite conductivity type to the first conductivity type of the active layer to be in contact with the surface of the CMOS isolation layer; and forming a second source layer and a second drain layer having the same conductivity type as the first conductivity type of the active layer to be spaced apart from each other in a surface layer portion of the second well layer, and wherein said forming a contact exposing impurity layer is simultaneously performed with at least one of said forming a first well layer, said forming a second well layer, said forming a first source layer, said forming a first drain layer, said forming a second source layer, and said forming a second drain layer.
28. The method of claim 23 , wherein said forming a transistor buried impurity layer comprises forming a collector layer as the transistor buried impurity layer having the same conductivity type as the first conductivity type of the active layer, said forming a transistor element comprises forming a bipolar transistor having the collector layer, and said forming a contact buried impurity layer is simultaneously performed with said forming a collector layer.
29. The method of claim 28 , wherein said forming a transistor element further comprises forming a transistor exposing impurity layer to form a first portion of the surface of the active layer on the transistor buried impurity layer by selectively implanting a first impurity into the element region from the surface of the active layer once the transistor buried impurity layer is formed, wherein said forming a substrate contact further comprises forming a contact exposing impurity layer to form a second portion of the surface of the active layer on the contact buried impurity layer by selectively implanting a second impurity into the contact region simultaneously when implanting the first impurity into the element region, wherein said forming a transistor exposing impurity layer comprises: forming a base layer as the transistor exposing impurity layer having an opposite conductivity type to the first conductivity type of the active layer to form a space between the base layer and the collector layer; and forming an emitter layer having the same conductivity type as the first conductivity type of the active layer in a surface layer portion of the base layer, wherein said forming a contact exposing impurity layer is simultaneously performed with at least one of said forming a base layer and said forming an emitter layer.
30. The method of claim 29 , wherein said forming a transistor exposing impurity layer comprises forming a sinker layer as the transistor exposing impurity layer having the same conductivity layer as the first conductivity type of the active layer, and the sinker layer extends from the surface of the active layer to reach the collector layer, and said forming a contact exposing impurity layer is simultaneously performed with said forming a sinker layer.
31. The method of claim 23 , wherein said forming a trench comprises: forming a half trench extending from the surface of the active layer to the buried insulation layer through dry etching; and removing the buried insulation layer forming a bottom wall of the half trench through wet etching.
32. The method of claim 23 , further comprising: forming a lower implanted layer on the support substrate by implanting an impurity into the bottom wall of the trench before the through contact is embedded once the trench reaching the support substrate is formed.
33. The method of claim 23 , further comprising: simultaneously forming an element isolating portion for insulating the element region from other portions of the active layer, and a contact isolating portion for insulating the contact region from other portions of the active layer once the trench reaching the support substrate is formed.
34. The method of claim 33 , wherein said forming an element isolating portion and a contact isolating portion comprises: forming annular deep trenches extending from the surface of the active layer to reach the buried insulation layer to surround each of the element region and the contact region; forming an insulation film on an inner wall of each of the deep trenches; and charging a semiconductor layer within each of the deep trenches.
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February 23, 2012
April 8, 2014
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