A nitride-based semiconductor substrate may includes a plurality of hollow member patterns arranged on a substrate, a nitride-based seed layer formed on the substrate between the plurality of hollow member patterns, and a nitride-based buffer layer on the nitride-based seed layer so as to cover the plurality of hollow member patterns, wherein the plurality of hollow member patterns contact the substrate in a first direction and both ends of each of the plurality of hollow member patterns are open in the first direction.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A nitride-based semiconductor substrate comprising: a plurality of hollow member patterns on a substrate, each of the plurality of hollow member patterns having a convex surface, a concave surface, and opposing open ends, the concave surface facing the substrate; a nitride-based seed layer on the substrate between each of the plurality of hollow member patterns; and a nitride-based buffer layer covering the plurality of hollow member patterns, wherein the plurality of hollow member patterns are aligned on the substrate in a first direction such that the opposing ends of each of the plurality of hollow member patterns are open in the first direction, and the plurality of hollow member patterns contact the substrate.
2. The nitride-based semiconductor substrate of claim 1 , wherein the substrate is formed of a material selected from the group consisting of silicon, sapphire, silicon carbide, glass, and a III-V group material.
3. The nitride-based semiconductor substrate of claim 1 , wherein the plurality of hollow member patterns are aligned so as to be parallel to the first direction and spaced apart from one another.
4. The nitride-based semiconductor substrate of claim 1 , wherein the nitride-based seed layer has a height lower than that of the plurality of hollow member patterns and has a thickness of about 5 nm-1 μm.
5. The nitride-based semiconductor substrate of claim 1 , wherein a cross-section of each of the plurality of hollow member patterns has any one of a rectangular shape, a trapezoidal shape, and a hemispherical shape.
6. A nitride-based semiconductor substrate comprising: a nitride-based seed layer on a substrate; a plurality of hollow member patterns on the nitride-based seed layer, each of the plurality of hollow member patterns having a convex surface, a concave surface, and opposing open ends, the concave surface facing the substrate; and a nitride-based buffer layer covering the plurality of hollow member patterns, wherein the plurality of hollow member patterns are aligned on the substrate in a first direction such that the opposing ends of each of the plurality of hollow member patterns are open in the first direction, and a lowermost portion of each of the plurality of hollow member patterns being above an uppermost portion of the nitride-based seed layer.
7. The nitride-based semiconductor substrate of claim 6 , wherein the substrate is formed of a material selected from the group consisting of silicon, sapphire, silicon carbide, glass, and a III-V group material.
8. The nitride-based semiconductor substrate of claim 6 , wherein the plurality of hollow member patterns are aligned so as to be parallel to the first direction and spaced apart from one another.
9. The nitride-based semiconductor substrate of claim 6 , wherein the nitride-based seed layer has a height lower than that of the plurality of hollow member patterns and has a thickness of about 5 nm-1 μm.
10. The nitride-based semiconductor substrate of claim 6 , wherein a cross-section of each of the plurality of hollow member patterns has any one of a rectangular shape, a trapezoidal shape, and a hemispherical shape.
11. A nitride-based semiconductor substrate comprising: a plurality of nitride-based seed layer patterns on a substrate; a plurality of hollow member patterns on the substrate, each of the plurality of hollow member patterns having a convex surface, a concave surface, and opposing open ends, the concave surface facing the substrate, each of the plurality of hollow member patterns being between a pair of adjacent nitride-based seed layer patterns; and a nitride-based buffer layer covering the plurality of hollow member patterns and the plurality of nitride-based seed layer patterns, wherein the plurality of hollow member patterns are aligned in a first direction such that the opposing ends of each of the plurality of hollow member patterns are open in the first direction, and the concave surface of each of the plurality of hollow member patterns, side surfaces of the pair of adjacent nitride-based seed layer patterns, and the substrate defining a cavity therebetween.
12. The nitride-based semiconductor substrate of claim 11 , wherein the plurality of nitride-based seed layer patterns are in the form of strips.
13. The nitride-based semiconductor substrate of claim 11 , wherein the substrate is formed of a material selected from the group consisting of silicon, sapphire, silicon carbide, glass, and a III-V group material.
14. The nitride-based semiconductor substrate of claim 11 , wherein the plurality of hollow member patterns are aligned so as to be parallel to the first direction and spaced apart from one another.
15. The nitride-based semiconductor substrate of claim 11 , wherein each of the plurality of nitride-based seed layer patterns has a height lower than that of the plurality of hollow member patterns and has a thickness of about 5 nm-1 μm.
16. The nitride-based semiconductor substrate of claim 11 , wherein a cross-section of each of the plurality of hollow member patterns has any one of a rectangular shape, a trapezoidal shape, and a hemispherical shape.
17. The nitride-based semiconductor substrate of claim 1 , wherein each of the plurality of hollow member patterns extends into the nitride-based buffer layer.
18. The nitride-based semiconductor substrate of claim 1 , wherein portions of the nitride-based buffer layer are between adjacent pairs of the plurality of hollow member patterns.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
April 1, 2011
April 15, 2014
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