Methods of dicing substrates having a plurality of ICs. A method includes forming a mask comprising a water soluble material layer over the semiconductor substrate. The mask is patterned with a femtosecond laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the substrate between the ICs. The substrate is then etched through the gaps in the patterned mask to singulate the IC and the water soluble material layer washed off.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of dicing a substrate comprising a plurality of ICs, the method comprising: forming a mask over the substrate covering and protecting the ICs, the mask comprising a layer of water soluble material in contact with a top surface of the ICs; patterning the mask and a portion of the substrate with a laser scribing process to provide a patterned mask and substrate with gaps, exposing regions of the substrate between the ICs, wherein each gap has a width in the substrate; and plasma etching through the gaps to form trenches in the substrate and to singulate the ICs, wherein each trench has the width.
2. The method of claim 1 , wherein patterning the mask with the laser scribing process comprises forming the gaps with a femtosecond laser, and wherein the water soluble material comprises a water soluble polymer, and wherein etching the semiconductor substrate comprises etching to form the trenches with a deep trench etch process during which the water soluble material is maintained below 100° C.
3. The method of claim 2 , wherein patterning the mask with the femtosecond laser scribing process comprises using a laser having a wavelength less than or equal to 530 nanometers and a laser pulse width less than or equal to 500 femtoseconds.
4. The method of claim 1 , wherein forming the mask further comprises forming the water soluble material layer to a thickness of no more than 20 microns over a street between the ICs and at least 10 μm over a top bump surface of an IC.
5. The method of claim 1 , wherein the forming the mask comprises applying at least one of: poly(vinyl alcohol), poly(acrylic acid), poly(methacrylic acid), poly(acrylamide), or poly(ethylene oxide) in contact with the top surface of the IC.
6. The method of claim 5 , wherein forming the mask comprises applying poly(vinyl alcohol) in contact with the top surface of the IC.
7. The method of claim 1 , wherein the applying comprises: spin coating an aqueous solution of a water soluble polymer on to the top surface of the IC; and drying the aqueous solution.
8. The method of claim 7 , further comprising thinning the substrate with a backside grind process, wherein the spin coating is performed after the backside grind.
9. The method of claim 1 , wherein the applying comprises: vacuum laminating a dry film of the water soluble material on to the top surface of the IC.
10. The method of claim 1 , further comprising thinning the substrate with a backside grind process, wherein the vacuum laminating is performed after the backside grind.
11. The method of claim 1 , further comprising removing the water soluble mask after plasma etching the substrate with an aqueous solution.
12. The method of claim 11 , wherein the removing comprises rinsing off the water soluble mask with a pressurized jet of water.
13. A method of dicing a semiconductor substrate comprising a plurality of ICs, the method comprising: forming a water soluble mask over a silicon substrate, the water soluble mask covering and protecting ICs disposed on the silicon substrate, the ICs comprising a thin film stack including a layer of silicon dioxide, a layer of low-k material and a layer of copper; patterning the water soluble mask, the layer of low-k material, the layer of copper, and a portion of the silicon substrate with a femtosecond laser to create gaps therein and to expose regions of the silicon substrate between the ICs, wherein each gap has a width in the silicon substrate; and plasma etching the silicon substrate through the gaps to form trenches in the silicon substrate and to singulate the ICs, wherein each trench has the width in the silicon substrate.
14. The method of claim 13 , wherein patterning the layer of silicon dioxide, the layer of low-k material, and the layer of copper with the femtosecond laser comprises ablating the layer of silicon dioxide prior to ablating the layer of low-k material and the layer of copper and wherein etching the silicon substrate comprises exposing the substrate to a plasma of SF 6 and at least one of C 4 F 8 and C 4 F 6 while maintaining the water soluble material layer at a temperature below 100° C.
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June 15, 2011
April 22, 2014
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