Substrate structures and methods of manufacturing the substrate structures. A substrate structure is manufactured by forming a protrusion area of a substrate under a buffer layer, and forming a semiconductor layer on the buffer layer, thereby separating the substrate from the buffer layer except in an area where the protrusion is formed. The semiconductor layer on the buffer layer not contacting the substrate has freestanding characteristics, and dislocation or cracks may be reduced and/or prevented.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A substrate structure comprising: a substrate including a plurality of substrate protrusions; a plurality of buffer layers on the plurality of substrate protrusions respectively, the plurality of substrate protrusions separating the plurality of buffer layers from a part of the substrate, at least one of the plurality of substrate protrusions having a width at a center that is less than a width at ends; and a semiconductor layer on the plurality of buffer layers, wherein the semiconductor layer extends across the plurality of buffer layers, and a lowermost surface of the semiconductor layer is at a height substantially equal to an uppermost surface of at least one of the plurality of buffer layers.
2. The substrate structure of claim 1 , wherein the semiconductor layer is a nitride semiconductor layer, and the nitride semiconductor layer extends across the plurality of buffer layers.
3. The substrate structure of claim 1 , wherein a shape of at least one of the plurality of buffer layers is one of polygonal, oval, and straight plate.
4. The substrate structure of claim 1 , wherein the width of one of the plurality of substrate protrusions increases as a function of distance from the center.
5. The substrate structure of claim 1 , wherein the substrate includes at least one of Si, GaN, sapphire, SiC, LiGaO 2 , ZrB 2 , ZnO and (Mn, Zn)FeO 4 .
6. The substrate structure of claim 1 , wherein the plurality of buffer layers have one of a single layer structure and a multi-layer structure, a material of the plurality of buffer layers includes at least one of AlN, SiC, Al 2 O 3 , AlGaN, AlInGaN, AlInBGaN, AlBGaN, GaN, and XY, X is at least one of Ti, Cr, Zr, Hf, Nb and Ta, and Y is at least one of nitrogen (N) and boron (B, B 2 ).
7. The substrate structure of claim 1 , wherein a thickness of the plurality of buffer layers is from about 5 nm to about 5 μm.
8. The substrate structure of claim 1 , wherein a width of a region separating the plurality of buffer layers is greater than about 10 nm.
9. The substrate structure of claim 1 , wherein a lowermost surface of the semiconductor layer is at a height substantially equal to an uppermost surface of at least one of the plurality of buffer layers.
10. The substrate structure of claim 1 , further comprising: an LED structure or a HEMT structure on the semiconductor layer.
11. A method of manufacturing a substrate structure, the method comprising: forming a buffer layer material on a substrate; etching a pattern into the buffer layer material to form a plurality of buffer layers that expose portions of the substrate; etching the substrate through the plurality of buffer layer to form a plurality of substrate protrusions, the plurality of substrate protrusions separating a part of the plurality of buffer layers from a part of the substrate; and forming a semiconductor layer on the plurality of buffer layers, the semiconductor layer extends across the plurality of buffer layers, and a lowermost surface of the semiconductor layer is at a height substantially equal to an uppermost surface of at least one of the plurality of buffer layers.
12. The method of claim 11 , further comprising: forming an etch mask on the buffer layer material, wherein the etching of the pattern into the buffer layer material includes anisotropically etching the buffer layer material through the etch mask to form the plurality of buffer layers that expose the portions of the substrate.
13. The method of claim 12 , wherein the etching of the substrate through the plurality of buffer layers includes anisotropically etching the substrate to form a substrate recess and isotropically etching the substrate recess to expose a part of a lower surface of the plurality of buffer layers.
14. The method of claim 11 , wherein a width of a surface of one of the plurality of substrate protrusions contacting a corresponding one of the plurality of buffer layers is smaller than a width of the corresponding one of the plurality of buffer layers.
15. The method of claim 11 , wherein the etching of the pattern into the buffer layer material includes separating the buffer layer material into the plurality of buffer layers, and the forming of the semiconductor layer includes forming the semiconductor layer as a single semiconductor layer supported by the plurality of buffer layers.
16. The method of claim 15 , wherein the forming of the semiconductor layer includes forming the semiconductor layer using an epitaxial lateral over growth (FLOG) process.
17. The method of claim 11 , wherein the etching of the pattern into the buffer layer material includes separating the buffer layer material into the plurality of buffer layers, and the forming of the semiconductor layer includes forming the semiconductor layer as a plurality of semiconductor layers, each of the plurality of semiconductor layers formed on a different one of the plurality of buffer layers.
18. The method of claim 17 , wherein the forming of the semiconductor layer on the plurality of buffer layers includes forming the semiconductor layer using a vertical growth process.
19. The method of claim 11 , further comprising: treating exposed surfaces of the substrate and the plurality of substrate protrusions by performing at least one of an oxidization process, a nitridization process, and an AlN layer forming process.
20. An electronic device, comprising: a substrate including a plurality of protrusions having concave side portions; a plurality of buffer layers on the plurality of protrusions respectively, a combined width of the plurality of buffer layers being greater than a combined width of the plurality of protrusions; and a semiconductor layer on the plurality of buffer layers, a lowermost surface of the semiconductor layer being at a height substantially equal to an uppermost surface of at least one of the plurality of buffer layers, the semiconductor layer extending across the plurality of buffer layers.
21. The electronic device of claim 20 , further comprising: a semiconductor layer on the plurality of buffer layers; a first electrode on the semiconductor layer; a pair of cladding layers on a part of the semiconductor layer not covered by the first electrode; an active layer between the pair of cladding layers; and a second electrode on the pair of cladding layers.
22. The electronic device of claim 20 , further comprising: an LED structure or a HEMT structure on the semiconductor layer.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
August 12, 2010
May 6, 2014
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