A programming method and memory structure for preventing punch-through in a short channel source-side select gate structure includes adjusting voltages on the selected and unselected bitlines, and the program, pass, and select gate voltages.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for operating a memory, comprising: biasing a well voltage of a selected string of memory cells to a first voltage; biasing a selected bit line of the selected string of memory cells to a second voltage; and biasing a source of the selected string of memory cells to a third voltage; wherein the second and third voltages are substantially equal to each other, and greater than the first voltage.
2. The method of claim 1 , wherein the second voltage is greater than 0 volts.
3. The method of claim 1 , and further comprising biasing an unselected bit line of an unselected string of memory cells to a fourth voltage, wherein the fourth voltage is greater than the second voltage.
4. The method of claim 1 , wherein the first voltage is less than 0 volts.
5. The method of claim 1 , wherein second and third voltages are each approximately 1.5 volts.
6. The method of claim 1 , wherein the first voltage is 0 volts.
7. The method of claim 3 , wherein the fourth voltage is greater than the second voltage by approximately 2 volts.
8. The method of claim 1 , and further comprising: biasing pass, program, and select gates of the memory to the first voltage.
9. A memory, comprising: an array of memory cells; and a controller for control and/or access of the array of memory cells, the controller adapted to perform a method comprising: biasing a well voltage of a selected string of memory cells to a first voltage; biasing a selected bit line of the selected string of memory cells to a second voltage; and biasing a source of the selected string of memory cells to a third voltage; wherein the second and third voltages are substantially equal to each other, and greater than the first voltage.
10. The memory of claim 9 , wherein the controller is further adapted to bias the selected bit line to a voltage greater than 0 volts.
11. The memory of claim 9 , wherein the controller is further adapted to bias an unselected bit line of an unselected string of memory cells to a fourth voltage, wherein the fourth voltage is greater than the second voltage.
12. The memory of claim 11 , wherein the controller is further adapted to bias the unselected bit line to a voltage greater than the selected bit line by approximately 2 volts.
13. The memory of claim 9 , wherein the controller is further adapted to bias the well to a voltage less than 0 volts.
14. The memory of claim 9 , wherein the controller is further adapted to bias the selected bit line and the source to approximately 1.5 volts.
15. The memory of claim 9 , wherein the controller is further adapted to bias the well to 0 volts.
16. The memory of claim 9 , wherein the controller is further adapted to bias pass, program, and select gates of the memory to the first voltage.
17. A method for operating a memory, comprising: biasing a well of a selected string of memory cells to a first voltage; biasing a selected bit line of the selected string of memory cells to a second voltage; and biasing a source of the selected string of memory cells to a third voltage; wherein the second and third voltages are substantially equal to 0 volts, and greater than the first voltage; and biasing an unselected bit line of an unselected string of memory cells to a fourth voltage, wherein the fourth voltage is greater than the second voltage.
18. The method of claim 17 , wherein the first voltage is a negative voltage.
19. The method of claim 17 , wherein the fourth voltage is greater than the second voltage by approximately 2 volts.
20. The method of claim 17 , wherein the fourth voltage is greater than the first voltage by approximately 3.5 volts.
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July 16, 2012
May 6, 2014
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