A method for making a semiconductor device comprises forming an electrical interconnect layer, forming a first dielectric layer over the interconnect layer, forming an opening in the first dielectric layer over a first electrical interconnect of the interconnect layer, forming an aluminum layer over the first dielectric layer, etching the aluminum layer to form an aluminum die pad, forming a second dielectric layer over the aluminum die pad and the first dielectric layer, and forming a conductive via through the first and second dielectric layers to contact a second electrical interconnect of the interconnect layer.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for making a semiconductor device comprising: forming an electrical interconnect layer; forming a first dielectric layer over the electrical interconnect layer; forming an opening in the first dielectric layer over a first interconnect of the electrical interconnect layer; forming an aluminum layer over the opening and the first dielectric layer; patterning the aluminum layer to form an aluminum die pad electrically coupled to the first interconnect of the electrical interconnect layer; forming a second dielectric layer with a planar surface over the aluminum die pad and the first dielectric layer; forming a conductive via through the first dielectric layer and the second dielectric layer to electrically contact a second interconnect of the electrical interconnect layer; after forming the conductive via, forming an opening in the second dielectric layer to expose at least a portion of the aluminum die pad, wherein a top surface of the aluminum die pad is at a level that is below a top surface of the conductive via.
2. The method of claim 1 wherein the forming a second dielectric layer with a planar surface includes forming the second dielectric layer and then planarizing the second dielectric layer.
3. A method for making a semiconductor device comprising: forming an electrical interconnect layer; forming a first dielectric layer over the electrical interconnect layer; forming an opening in the first dielectric layer over a first interconnect of the electrical interconnect layer; forming an aluminum layer over the opening and the first dielectric layer; patterning the aluminum layer to form an aluminum die pad electrically coupled to the first interconnect of the electrical interconnect layer; forming a second dielectric layer with a planar surface over the aluminum die pad and the first dielectric layer; forming a conductive via through the first dielectric layer and the second dielectric layer to electrically contact a second interconnect of the electrical interconnect layer; wherein the forming a second dielectric layer with a planar surface includes forming the second dielectric layer and then planarizing the second dielectric layer; before planarizing the second dielectric layer, forming a layer of photo resist over the second dielectric layer; forming an opening in the layer of photo resist to the second dielectric layer above an inner area of the aluminum die pad; and etching the second dielectric layer, wherein the etching results in a raised portion of the second dielectric layer around at least a portion of the inner area of the aluminum die pad.
4. The method of claim 1 further comprising: forming a transistor on a substrate, the transistor is located below the electrical interconnect layer.
5. The method of claim 1 further comprising: forming at least one electrical interconnect layer, the at least one electrical interconnect layer is located below the electrical interconnect layer.
6. The method of claim 1 further comprising: bonding an electrically conductive structure to the aluminum die pad after forming the conductive via.
7. The method of claim 1 wherein: the aluminum die pad extends over sides of the opening in the first dielectric layer.
8. The method of claim 1 further comprising: forming a structure over the conductive via and electrically coupled to the conductive via.
9. The method of claim 1 wherein: a top surface of the conductive via is coplanar with the planar surface of the second dielectric layer or a planar surface above the planar surface of the second dielectric layer.
10. The method of claim 1 wherein the first interconnect and the second interconnect are electrically coupled.
11. The method of claim 3 further comprising: after forming the conductive via, forming an opening in the second dielectric layer to expose at least a portion of the aluminum die pad, wherein a top surface of the aluminum die pad is at a level that is below a top surface of the conductive via.
12. A method for making a semiconductor device comprising: forming an interconnect layer including a first electrical interconnect; forming a first dielectric layer over the interconnect layer; forming an opening in the first dielectric layer and over the first electrical interconnect of the interconnect layer; forming an aluminum layer in the opening and over the first dielectric layer; etching the aluminum layer to form an aluminum die pad over the first electrical interconnect, the aluminum die pad electrically coupled to the first electrical interconnect; forming a second dielectric layer over the aluminum die pad and the first dielectric layer; and planarizing the second dielectric layer to form a planar surface; forming a conductive via through the first dielectric layer and the second dielectric layer to electrically contact a second electrical interconnect of the interconnect layer; after forming the conductive via, forming an opening in the second dielectric layer to expose at least a portion of the aluminum die pad, wherein a to surface of the aluminum die pad is at a level that is below a to surface of the conductive via.
13. The method of claim 3 wherein a top surface of the aluminum die pad is at a level that is below a top surface of the conductive via.
14. The method of claim 12 wherein: the forming an opening in the second dielectric layer to expose at least a portion of the aluminum die pad is performed after the planarizing the second dielectric layer.
15. The method of claim 12 further comprising: forming a transistor on a substrate, the transistor is located below the interconnect layer; forming a plurality of interconnect layers, the plurality of interconnect layers is located between the substrate and the interconnect layer; and forming a barrier layer over the first dielectric layer and the opening in the first dielectric layer before forming the aluminum layer.
16. The method of claim 12 wherein: the aluminum die pad extends over sides of the opening in the first dielectric layer.
17. The method of claim 12 further comprising: forming a structure over the planar surface; wherein the forming an opening in the second dielectric layer to expose at least a portion of the aluminum die pad is performed after forming the structure.
18. A method for making a semiconductor device comprising: forming an electrical interconnect layer; forming a first dielectric layer over the electrical interconnect layer; forming an opening in the first dielectric layer over a first electrical interconnect of the electrical interconnect layer; forming an aluminum layer in the opening and over the first dielectric layer; etching the aluminum layer to form an aluminum die pad, the aluminum die pad electrically coupled to the first electrical interconnect; forming a second dielectric layer over the aluminum die pad and the first dielectric layer; and forming a conductive via through the first dielectric layer and the second dielectric layer to contact a second electrical interconnect of the electrical interconnect layer; after forming the conductive via, forming an opening in the second dielectric layer to expose at least a portion of the aluminum die pad, wherein a to surface of the aluminum die pad is at a level that is below a to surface of the conductive via.
19. The method of claim 18 further comprising: planarizing the second dielectric layer; and after the planarizing, forming a stop layer over the second dielectric layer.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
July 28, 2011
May 13, 2014
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