Pattern matching appratus

1. A pattern matching apparatus comprising: a configuration controller configuring configuration data with a certain format, which corresponds to an arbitrary regular expression combining characters as text characters and metacharacters having certain functional meanings; and an automaton circuit being realized by a hardware circuit, performing configuration, which is reconfigurable, corresponding to said regular expression by storing said configuration data in said hardware circuit, and being used for carrying out pattern matching to said regular expression, wherein said automaton circuit includes: character node circuit sections storing data corresponding to characters of said regular expression, metacharacter node circuit sections storing data corresponding to metacharacters of said regular expression and configure connection relations to said character node circuit sections by using said stored data, said metacharacter node circuit sections configuring connection relations to said other metacharacter node circuit sections by using said stored data, and switch node circuit sections configuring connection relations between metacharacter node circuit sections.

2. The pattern matching apparatus according to claim 1 , wherein the total amount of said character node circuit sections is larger than the total amount of said metacharacter node circuit sections by one, wherein each of said character node circuit sections and each of said metacharacter node circuit sections are arranged alternately one by one in series, wherein each of said metacharacter node circuit sections is connected to two of said character node circuit sections adjacent to a left and right of said each metacharacter node circuit section, and wherein two of said metacharacter node circuit sections connected to an identical character node circuit section of said character node circuit sections are connected to each other.

3. The pattern matching apparatus according to claim 2 , wherein said switch node circuit sections connect between said metacharacter node circuit sections except for two of said metacharacter node circuit sections connected to an identical character node circuit section of said character node circuit sections, wherein said connection relations in said switch node circuit sections have shapes of M-ary trees including said metacharacter node circuit sections as leaf nodes, wherein when the total number of said metacharacter node circuit sections is N, the total number of said M-ary trees is the double of a minimum integer which is not less than log 2 (N+1)−1.

4. The pattern matching apparatus according to claim 3 , further comprising: multiplexer circuit sections being used for integrating a plurality of signals output toward an identical metacharacter node from different switch node circuit sections in said M-ray trees, and wherein each of said multiplexer circuit sections corresponds to one of said metacharacter node circuit sections one to one.

5. The pattern matching apparatus according to claim 4 , wherein each of said metacharacter node circuit sections includes: five input sections receiving five input signals, respectively, from said corresponding multiplexer circuit section, a metacharacter node circuit section connected to the left side, a metacharacter node circuit section connected to the right side, a character node circuit section connected to the left side and a character node circuit section connected to the right side, five output sections outputting output signals, respectively, to said corresponding multiplexer circuit section, a metacharacter node circuit section connected to the left side, a metacharacter node circuit section connected to the right side, a character node circuit section connected to the left side and a character node circuit section connected to the right side, and five switch circuit sections connecting to said five output sections, respectively, wherein said five switch circuit sections output results of respective logic operations for said five input signals, wherein said configuration data includes setting values with respect to logic operations respectively performed by said five switch circuit sections.

6. The pattern matching apparatus according to claim 3 , wherein when, in a certain integer n, the total number of said metacharacter node circuit sections is more than M n−1 and equal to or less than (M n , the total number of said switch node circuit sections of one of said M-ary trees is equal to or less than (M n− 1)/(M−1).

7. The pattern matching apparatus according to claim 6 , wherein each of said switch node circuit sections includes: (M+1) input sections receiving signals, respectively, from a previous stage switch node circuit section and M metacharacter node circuit sections or from a previous stage switch node circuit section and M later stage switch node circuit sections, (M+1) output sections outputting signals, respectively, to a previous stage switch node circuit section and MUXs corresponding to M metacharacter node circuit sections or to a previous stage switch node circuit section and M later stage switch node circuit sections, and (M+1) switch circuit sections connecting to said (M+1) output sections, respectively, wherein each of said (M+1) switch circuit sections selectively outputs one of input signals from circuit sections except for a circuit section which is connected to the corresponding output section, and wherein said configuration data includes setting values of selections respectively performed by said (M+1) switch circuit sections.

8. The pattern matching apparatus according to claim 6 , wherein said M-ary trees comprise binary trees.

9. The pattern matching apparatus according to claim 6 , wherein said M-ary trees comprise quadtrees.

10. The pattern matching apparatus according to claim 2 , wherein each of said character node circuit sections comprises: a first input section receiving an output signal of a metacharacter node circuit section connected to the left side, a second input section receiving an output signal of a metacharacter node circuit section connected to the right side, a first switch circuit section selectively outputting one of a first input signal received by said first input section and a second input signal received by said second input section, a flip-flop circuit section storing an output signal of said first switch circuit section, a third input section receiving text character data for performing pattern matching, a comparator circuit section comparing said text character data with a character stored in said character node circuit section, a logical AND circuit section calculating logical AND between an output signal of the comparator circuit section and an output signal of the flip-flop circuit section, a second switch circuit section selectively outputting one of an output signal of said logical AND circuit section, said first input signal and said second input signal, and an output section outputting an output signal from said second switch circuit section, wherein said configuration data includes: a setting value of selection performed by said first switch circuit section, a setting value of selection performed by said second switch circuit section, and character data stored in said character node circuit section.

11. The pattern matching apparatus according to claim 2 , wherein each of said character node circuit sections comprises: a first input section receiving an output signal of a metacharacter node circuit section connected to the left side, a second input section receiving an output signal of a metacharacter node circuit section connected to the right side, a first switch circuit section selectively outputting one of a first input signal received by said first input section, a second input signal received by said second input section and a third input signal, a flip-flop circuit section storing an output signal of said first switch circuit section, a third input section receiving text character data for performing pattern matching, a comparator circuit section comparing said text character data with a character stored in said character node circuit section, a logical AND circuit section calculating logical AND between an output signal of the comparator circuit section and an output signal of the flip-flop circuit section as said third signal, a second switch circuit section selectively outputting one of an output signal of said logical AND circuit section, said first input signal and said second input signal, and an output section outputting an output signal from said second switch circuit section, wherein said configuration data includes: a setting value of selection performed by said first switch circuit section, a setting value of selection performed by said second switch circuit section, and character data stored in said character node circuit section.

12. The pattern matching apparatus according to claim 11 , wherein said first switch circuit section includes: a first memory circuit section storing a setting value for selecting one of said first input section and said second input section, a third switch circuit section selectively outputting one of said first input section and said second input section based on said setting value stored in said first memory circuit section, a second memory circuit section storing information regarding whether or not a character stored in said character node circuit section is merged with a metacharacter “*” indicating matching up 0 times or more, a logical AND circuit section calculating logical AND between said third signal and an output signal of said second memory circuit section, and a logical OR circuit section calculating logical OR between an output signal of said logical AND circuit section and an output signal of said third switch circuit section to output toward said flip-flop circuit section, wherein said second switch circuit section includes: a third memory circuit section storing a setting value of selection performed by said second switch circuit section and connecting to said second switch circuit section, and wherein said pattern matching apparatus further comprising: a fourth memory circuit section storing data of a character stored in the character node circuit section and connecting to said comparator circuit section.

13. The pattern matching apparatus according to claim 1 , further comprising: a storage device connecting to said configuration controller and storing said configuration data.

14. An automaton circuit in a pattern matching apparatus, wherein said pattern matching apparatus includes: a configuration controller configuring configuration data with a certain format, which corresponds to an arbitrary regular expression combining characters as text characters and metacharacters having certain functional meanings, and said automaton circuit being realized by a hardware circuit, performing configuration, which is reconfigurable, corresponding to said regular expression by storing said configuration data in said hardware circuit, and being used for carrying out pattern matching to said regular expression, said automaton circuit comprising: character node circuit sections storing data corresponding to characters of said regular expression; metacharacter node circuit sections storing data corresponding to metacharacters of said regular expression and configure connection relations to said character node circuit sections by using said stored data, said metacharacter node circuit sections configuring connection relations to said other metacharacter node circuit sections by using said stored data; and switch node circuit sections configuring connection relations between metacharacter node circuit sections.

15. A pattern matching method comprising: (a) configuring configuration data with a certain format, which corresponds to an arbitrary regular expression combining characters as text characters and metacharacters having certain functional meanings; (α) performing configuration corresponding to said regular expression to an automaton circuit, which is realized by a hardware circuit, by storing said configuration data in a reconfigurable manner; and (b) carrying out pattern matching using said automaton circuit, wherein said (a) includes: (a-1) in character node circuit sections of said automaton circuit, storing data corresponding to characters of said regular expression, (a-2) in metacharacter node circuit sections of said automaton circuit, storing data corresponding to metacharacters of said regular expression and configuring connection relations to said character nodes or the other metacharacter nodes by using said stored data, and (a-3) in a switch node circuit section of said automaton circuit, configuring connection relations between said metacharacter nodes.

16. The automaton circuit according to claim 14 , wherein the total amount of said character node circuit sections is larger than the total amount of said metacharacter node circuit sections by one, wherein each of said character node circuit sections and each of said metacharacter node circuit sections are arranged alternately one by one in series, wherein each of said metacharacter node circuit sections is connected to two of said character node circuit sections adjacent to a left and right of said each metacharacter node circuit section, and wherein two of said metacharacter node circuit sections connected to an identical character node circuit section of said character node circuit sections are connected to each other.

17. The automaton circuit according to claim 16 , wherein said switch node circuit sections connect between said metacharacter node circuit sections except for two of said metacharacter node circuit sections connected to an identical character node circuit section of said character node circuit sections, wherein said connection relations in said switch node circuit sections have shapes of M-ary trees including said metacharacter node circuit sections as leaf nodes, wherein when the total number of said metacharacter node circuit sections is N, the total number of said M-ary trees is the double of a minimum integer which is not less than log 2 (N+1)−1.

18. The automaton circuit according to claim 17 , further comprising: multiplexer circuit sections being used for integrating a plurality of signals output toward an identical metacharacter node from different switch node circuit sections in said M-ray trees, and wherein each of said multiplexer circuit sections corresponds to one of said metacharacter node circuit sections one to one.

19. The automaton circuit according to claim 18 , wherein each of said metacharacter node circuit sections includes: five input sections receiving five input signals, respectively, from said corresponding multiplexer circuit section, a metacharacter node circuit section connected to the left side, a metacharacter node circuit section connected to the right side, a character node circuit section connected to the left side and a character node circuit section connected to the right side, five output sections outputting output signals, respectively, to said corresponding multiplexer circuit section, a metacharacter node circuit section connected to the left side, a metacharacter node circuit section connected to the right side, a character node circuit section connected to the left side and a character node circuit section connected to the right side, and five switch circuit sections connecting to said five output sections, respectively, wherein said five switch circuit sections output results of respective logic operations for said five input signals, wherein said configuration data includes setting values with respect to logic operations respectively performed by said five switch circuit sections.

20. The automaton circuit according to claim 17 , wherein when, in a certain integer n, the total number of said metacharacter node circuit sections is more than M n−1 and equal to or less than M n , the total number of said switch node circuit sections of one of said M-ary trees is equal to or less than (M n −1)/(M−1).

21. The automaton circuit according to claim 20 , wherein each of said switch node circuit sections includes: (M+1) input sections receiving signals, respectively, from a previous stage switch node circuit section and M metacharacter node circuit sections or from a previous stage switch node circuit section and M later stage switch node circuit sections, (M+1) output sections outputting signals, respectively, to a previous stage switch node circuit section and MUXs corresponding to M metacharacter node circuit sections or to a previous stage switch node circuit section and M later stage switch node circuit sections, and (M+1) switch circuit sections connecting to said (M+1) output sections, respectively, wherein each of said (M+1) switch circuit sections selectively outputs one of input signals from circuit sections except for a circuit section which is connected to the corresponding output section, and wherein said configuration data includes setting values of selections respectively performed by said (M+1) switch circuit sections.

22. The automaton circuit according to claim 20 , wherein said M-ary trees comprise binary trees.

23. The automaton circuit according to claim 20 , wherein said M-ary trees comprise quadtrees.

24. The automaton circuit according to claim 16 , wherein each of said character node circuit sections: a first input section receiving an output signal of a metacharacter node circuit section connected to the left side, a second input section receiving an output signal of a metacharacter node circuit section connected to the right side, a first switch circuit section selectively outputting one of a first input signal received by said first input section and a second input signal received by said second input section, a flip-flop circuit section storing an output signal of said first switch circuit section, a third input section receiving text character data for performing pattern matching, a comparator circuit section comparing said text character data with a character stored in said character node circuit section, a logical AND circuit section calculating logical AND between an output signal of the comparator circuit section and an output signal of the flip-flop circuit section, a second switch circuit section selectively outputting one of an output signal of said logical AND circuit section, said first input signal and said second input signal, and an output section outputting an output signal from said second switch circuit section, wherein said configuration data includes: a setting value of selection performed by said first switch circuit section, a setting value of selection performed by said second switch circuit section, and character data stored in said character node circuit section.

25. The automaton circuit according to claim 16 , wherein each of said character node circuit sections comprises: a first input section receiving an output signal of a metacharacter node circuit section connected to the left side, a second input section receiving an output signal of a metacharacter node circuit section connected to the right side, a first switch circuit section selectively outputting one of a first input signal received by said first input section, a second input signal received by said second input section and a third input signal, a flip-flop circuit section storing an output signal of said first switch circuit section, a third input section receiving text character data for performing pattern matching, a comparator circuit section comparing said text character data with a character stored in said character node circuit section, a logical AND circuit section calculating logical AND between an output signal of the comparator circuit section and an output signal of the flip-flop circuit section as said third signal, a second switch circuit section selectively outputting one of an output signal of said logical AND circuit section, said first input signal and said second input signal, and an output section outputting an output signal from said second switch circuit section, wherein said configuration data includes: a setting value of selection performed by said first switch circuit section, a setting value of selection performed by said second switch circuit section, and character data stored in said character node circuit section.

26. The automaton circuit according to claim 25 , wherein said first switch circuit section includes: a first memory circuit section storing a setting value for selecting one of said first input section and said second input section, a third switch circuit section selectively outputting one of said first input section and said second input section based on said setting value stored in said first memory circuit section, a second memory circuit section storing information regarding whether or not a character stored in said character node circuit section is merged with a metacharacter “*” indicating matching up 0 times or more, a logical AND circuit section calculating logical AND between said third signal and an output signal of said second memory circuit section, and a logical OR circuit section calculating logical OR between an output signal of said logical AND circuit section and an output signal of said third switch circuit section to output toward said flip-flop circuit section, wherein said second switch circuit section includes: a third memory circuit section storing a setting value of selection performed by said second switch circuit section and connecting to said second switch circuit section, and wherein said pattern matching apparatus further comprising: a fourth memory circuit section storing data of a character stored in the character node circuit section and connecting to said comparator circuit section.