A method of fabricating a microelectronic unit can include providing a semiconductor element having front and rear surfaces, a plurality of conductive pads each having a top surface exposed at the front surface and a bottom surface remote from the top surface, and a first opening extending from the rear surface towards the front surface. The method can also include forming at least one second opening extending from the first opening towards the bottom surface of a respective one of the pads. The method can also include forming a conductive via, a conductive interconnect, and a contact, the conductive via in registration with and in contact with the conductive pad and extending within the second opening, the contact exposed at an exterior of the microelectronic unit, the conductive interconnect electrically connecting the conductive via with the contact and extending away from the via at least partly within the first opening.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of fabricating a microelectronic unit, comprising: providing a semiconductor chip having a front surface and a rear surface remote from the front surface, a microelectronic device including an active semiconductor region in a region of semiconductor material below the front surface, a plurality of conductive pads each having a top surface exposed at the front surface and having a bottom surface remote from the top surface, and a first opening extending from the rear surface towards the front surface, the first opening having an interior surface and a first layer formed on the surface; removing semiconductor material through an opening in the first layer to form at least one second opening extending from the first opening towards the bottom surface of a respective one of the pads; forming a second dielectric layer at least lining the second opening; removing at least a portion of a third dielectric layer contacting the bottom surface of the pad; and forming a conductive via, a conductive interconnect, and a contact, the conductive via in registration with and in contact with the conductive pad and extending within the second opening, the contact exposed at an exterior of the microelectronic unit, the conductive interconnect electrically connecting the conductive via with the contact and extending away from the via at least partly within the first opening, wherein the first opening has a first width in a lateral direction along the rear surface, the second opening has a second width in the lateral direction where the second opening meets the first opening, and the second opening has a third width in the lateral direction adjacent the conductive pad, the first width being greater than the second width, and the second width being greater than the third width.
2. The method as claimed in claim 1 , wherein the second dielectric layer includes a polymer.
3. The method as claimed in claim 2 , wherein the step of forming the second dielectric layer includes electrophoretically depositing a polymer conformally coating the interior surface of at least the second opening.
4. The method as claimed in claim 1 , further comprising forming the second dielectric layer by depositing dielectric material conformally coating an interior surface of at least the second opening.
5. The method as claimed in claim 2 , further comprising forming the opening in the first layer by photolithography.
6. The method as claimed in claim 5 , wherein the first layer includes a photoresist layer.
7. The method as claimed in claim 6 , further comprising removing the first layer prior to forming the second dielectric layer, wherein the step of forming the second dielectric layer includes forming the second dielectric layer on interior surfaces of the first and second openings.
8. The method as claimed in claim 1 , wherein the step of removing at least a portion of the third dielectric layer includes etching the third dielectric layer.
9. The method as claimed in claim 1 , wherein the step of forming the conductive interconnect includes forming a dielectric layer on at least the interior surface therein, and then filling a remaining volume of the first opening with a conductive material.
10. The method as claimed in claim 1 , wherein the step of forming the conductive via includes filling the second opening with a conductive material after forming the second dielectric layer.
11. The method as claimed in claim 1 , wherein the step of forming the conductive via includes depositing a conductive material conformally onto a surface of the second dielectric layer.
12. The method as claimed in claim 1 , wherein the step of forming the conductive interconnect includes depositing a conductive material conformally onto a surface of the second dielectric layer.
13. A method of fabricating a microelectronic unit, comprising: providing a semiconductor chip having a front surface and a rear surface remote from the front surface, a microelectronic device including an active semiconductor region in a region of semiconductor material below the front surface, and a first opening extending from the rear surface towards the front surface, the first opening having an interior surface and a first layer overlying the interior surface; removing semiconductor material from the front surface to form at least one second opening meeting the first opening; then forming a second dielectric layer at least lining the second opening; and forming a conductive via, a conductive element, a conductive interconnect, and a conductive contact, the conductive via extending within the second opening, the conductive element overlying the conductive via at the front surface, the contact exposed at an exterior of the microelectronic unit, and the conductive interconnect extending away from the via at least partly within the first opening and electrically connecting the via with the contact, wherein the first opening has a first width extending in a lateral direction along the rear surface, the second opening has a second width in the lateral direction where the second opening meets the first opening, and the second opening has a third width in the lateral direction adjacent the conductive element, such that the first and the third widths are greater than the second width.
14. The method as claimed in claim 13 , wherein the second dielectric layer includes a polymer.
15. The method as claimed in claim 14 , wherein the forming of at least one of the first and second dielectric layers includes electrophoretically depositing a polymer conformally coating an interior surface of at least one of the first opening or the second opening.
16. The method as claimed in claim 13 , further comprising forming the second dielectric layer by depositing dielectric material conformally coating an interior surface of at least the second opening.
17. The method as claimed in claim 14 , further comprising using a laser to form the opening in the first dielectric layer.
18. The method as claimed in claim 13 , wherein the step of forming the conductive via, the conductive element, the conductive interconnect and the contact includes filling the second opening with a conductive material, and forming the conductive element in contact therewith.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
November 8, 2012
May 27, 2014
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