A dual-gate transistor including: a first insulating layer provided to cover a first conductive layer; a first semiconductor layer over the first insulating layer; second semiconductor layers over the first semiconductor layer, the second semiconductor layers are spaced from each other to expose the first semiconductor layer; impurity semiconductor layers over the second semiconductor layers; second conductive layers over the impurity semiconductor layers; second insulating layers over the second conductive layers; a third insulating layer to cover the first semiconductor layer, the second semiconductor layers, the impurity semiconductor layers, the second conductive layers, and the second insulating layers; and a third conductive layer at least over the third insulating layer, and in the dual-gate transistor including the first to third insulating layers with openings, the first insulating layer is substantially equal in thickness to the second insulating layer.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for manufacturing a semiconductor device comprising the steps of: forming a first insulating layer over a first conductive layer; forming a first semiconductor layer over the first insulating layer; forming a second semiconductor layer over the first semiconductor layer; forming an impurity semiconductor layer over the second semiconductor layer; etching the impurity semiconductor layer, the second semiconductor layer and the first semiconductor layer with a first predetermined mask; forming a second conductive layer over the impurity semiconductor layer; forming a second insulating layer over the second conductive layer; etching the second insulating layer and the second conductive layer with a second predetermined mask to form a pair of second insulating layers and a pair of second conductive layers; etching the impurity semiconductor layer and the second semiconductor layer to form a pair of impurity semiconductor layers and a pair of second semiconductor layers so as to expose the first semiconductor layer between the pair of second semiconductor layers; forming a third insulating layer at least over the pair of second insulating layers, the first semiconductor layer and the first insulating layer; forming a first opening portion in the third insulating layer and the first insulating layer; forming a second opening portion in the third insulating layer and one of the pair of second insulating layers; and forming a third conductive layer over the third insulating layer, wherein a thickness of the first insulating layer is substantially equal to a thickness of the pair of second insulating layers.
2. A method for manufacturing a semiconductor device comprising the steps of: forming a first insulating layer over a first conductive layer; forming a first semiconductor layer over the first insulating layer; forming a second semiconductor layer over the first semiconductor layer; forming an impurity semiconductor layer over the second semiconductor layer; etching the impurity semiconductor layer, the second semiconductor layer and the first semiconductor layer with a first predetermined mask; forming a second conductive layer over the impurity semiconductor layer; forming a second insulating layer over the second conductive layer; etching the second insulating layer and the second conductive layer with a second predetermined mask to form a pair of second insulating layers and a pair of second conductive layers; etching the impurity semiconductor layer and the second semiconductor layer to form a pair of impurity semiconductor layers and a pair of second semiconductor layers so as to expose the first semiconductor layer between the pair of second semiconductor layers; forming a third insulating layer at least over the pair of second insulating layers, the first semiconductor layer and the first insulating layer; forming a first opening portion in the third insulating layer and the first insulating layer; forming a second opening portion in the third insulating layer and one of the pair of second insulating layers; and forming a third conductive layer over the third insulating layer, wherein a depth of the first opening portion is substantially equal to a depth of the second opening portion.
3. The method for manufacturing a semiconductor device according to claim 1 , wherein the second insulating layer and the second conductive layer are etched with a same etching step.
4. The method for manufacturing a semiconductor device according to claim 2 , wherein the second insulating layer and the second conductive layer are etched with a same etching step.
5. The method for manufacturing a semiconductor device according to claim 1 , wherein a thickness of the first insulating layer is 250 nm or more and 450 nm or less, and wherein a thickness of the third insulating layer is 60 nm or more and less than 250 nm.
6. The method for manufacturing a semiconductor device according to claim 2 , wherein a thickness of the first insulating layer is 250 nm or more and 450 nm or less, and wherein a thickness of the third insulating layer is 60 nm or more and less than 250 nm.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
August 22, 2011
May 27, 2014
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