Semiconductor device and method of controlling the same

1. A device comprising: a command decoder configured to output, in a normal operation mode, a precharge signal in response to a first type transition edge of a synchronous signal, and an active signal in response to a next first type transition edge that is next to the first type transition edge, and the command decoder configured to output, in a test mode, the precharge signal in response to a second type transition edge of the synchronous signal, and the active signal in response to a next first type transition edge that is next to the second type transition edge.

2. The device according to claim 1 , wherein the command decoder is configured to delay outputting the precharge signal by a half cycle of the synchronous signal, in the test mode.

3. The device according to claim 2 , further comprising: a test mode circuit coupled to the command decoder, the test mode circuit being configured to supply a test mode signal to the command decoder, wherein the command decoder is configured to delay supplying the precharge signal to the control circuit, upon receipt of the test mode signal from the test mode circuit.

4. The device according to claim 1 , further comprising: a control circuit coupled to the command decoder, wherein the command decoder is configured to supply the precharge signal to the control circuit, to enable the control circuit to perform precharge control, and wherein the command decoder is configured to supply the active signal to the control circuit, to enable the control circuit to start active control before the control circuit completes precharge control.

5. The device according to claim 1 , wherein the command decoder is configured to recognize activation of an internal circuit of the device in response to an input of an act command that is to activate the internal circuit, and the command decoder is configured to recognize inactivation of the internal circuit in response to an input of a precharge command that is to inactivate the internal circuit.

6. The device according to claim 1 , further comprising: a control circuit coupled to the command decoder, wherein the command decoder is configured to recognize and hold a precharge command that is to inactivate the device, in response to a first type transition edge of a first cycle of the synchronous signal, wherein the command decoder is configured to supply the precharge signal to the control circuit, in the test mode, in response to a second type transition of a second cycle next to the first cycle, wherein the command decoder is configured to recognize an active command that is to activate the device and supply the active signal to the control circuit, in response to a first type transition edge of the second cycle.

7. The device according to claim 6 , further comprising: a test mode circuit coupled to the command decoder, the test mode circuit being configured to recognize a mode register command in a first transition edge of a previous cycle previous to the first cycle, and supply a test mode signal to the command decoder.

8. The device according to claim 1 , wherein the command decoder comprises: a first capturing unit configured to recognize and hold active operation of the device in response to the first type transition edge of the synchronous signal; a first output unit coupled to the first capturing unit to receive the first signal from the first capturing unit and to output the first signal in response to the next first type transition edge that is next to the first type transition edge; a second capturing unit configured to recognize and hold inactive operation of the device in response to the first type transition edge of the synchronous signal; and a second output unit coupled to the second capturing unit to receive the second signal from the second capturing unit, wherein the second capturing unit is configured to output, in the normal operation mode, the second signal in response to the next first type transition edge, and wherein the second capturing unit is configured to output, in the test mode, the second signal in response to the second type transition edge that is next to the first type transition edge.

9. The device according to claim 8 , further comprising: a plurality of internal circuits; and a control circuit coupled to the command decoder, the control circuit being coupled to each of the plurality of internal circuits, the control circuit being configured to supply an activation signal or an inactivation signal to each of the plurality of internal circuits, in response to the first and second signals from the first and second output units, respectively.

10. The device according to claim 9 , wherein the control circuit is configured to output, upon input of the first signal, a selected one of the activation signal and the inactivation signal, the selection being performed in accordance with a respective operational state of each of the plurality of internal circuits, and wherein the control circuit is configured to output, upon input of the second signal, the other of the activation signal and the inactivation signal.

11. The device according to claim 8 , wherein the second output unit comprises: a first shift unit configured to shift the second signal by a half cycle of the synchronous signal.

12. The device according to claim 1 , wherein the command decoder comprises: a delay circuit configured to delay, in the test mode, outputting the precharge signal by a half cycle of the synchronous signal.

13. The device according to claim 1 , further comprising: a memory cell array; a row decoder coupled to the memory cell array; a sense amplifier coupled to the memory cell array; a column decoder coupled to the sense amplifier; and a control circuit coupled to the row decoder, the sense amplifier, and the column decoder, the control circuit being coupled to the command decoder to receive the precharge signal and the active signal from the command decoder.

14. A device comprising: a command decoder configured to output a precharge signal and an active signal in synchronous with a clock, wherein a first time period between outputting the precharge signal and outputting the active signal in a test mode is shorter than a second time period of between outputting the precharge signal and outputting the active signal in a normal operation mode.

15. The device according to claim 14 , wherein the command decoder is configured to output, in the normal operation mode, the precharge signal in response to a first type transition edge of the clock, the command decoder is configured to output, in the normal operation mode, the active signal in response to a next first type transition edge that is next to the first type transition edge, the command decoder is configured to output, in the test mode, the precharge signal in response to a second type transition edge of the clock, the second type transition edge being next to the first type transition edge, and the command decoder is configured to output, in the test mode, the active signal in response to the next first type transition edge.

16. The device according to claim 14 , wherein the first time period is a half of the second time period.

17. A method of controlling a device, the method comprising: in a normal operation mode, outputting a precharge signal in response to a first type transition edge of a synchronous signal, and an active signal in response to a next first type transition edge that is next to the first type transition edge, and in a test mode, outputting, the precharge signal in response to a second type transition edge of the synchronous signal, and the active signal in response to a next first type transition edge that is next to the second type transition edge.

18. The method according to claim 17 , further comprising: recognizing and holding a precharge command in response to a first type transition edge of a first cycle of the synchronous signal; in the test mode, supplying the precharge signal from the command decoder to a control circuit, in response to a second type transition of a second cycle next to the first cycle; recognizing and holding an active command that is to activate the device; and supplying the active signal from the command decoder to the control circuit, in response to a first type transition edge of the second cycle.

19. The method according to claim 17 , further comprising: recognizing a mode register command in a first transition edge of a previous cycle previous to the first cycle; and supplying a test mode signal to the command decoder.

20. The method according to claim 17 , further comprising: in the test mode, performing a delay in outputting the precharge signal by a half cycle of the synchronous signal, and in the normal operation mode, performing no delay in outputting the precharge signal.