The present invention provides a MEMS structure comprising confined sacrificial oxide layer and a bonded Si layer. Polysilicon stack is used to fill aligned oxide openings and MEMS vias on the sacrificial layer and the bonded Si layer respectively. To increase the design flexibility, some conductive polysilicon layer can be further deployed underneath the bonded Si layer to form the functional sensing electrodes or wiring interconnects. The MEMS structure can be further bonded to a metallic layer on top of the Si layer and the polysilicon stack.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A micro-electromechanical system (MEMS), comprising: a substrate; an isolation layer on top of the substrate, wherein the isolation layer comprises silicon nitride; a sacrificial layer on top of the isolation layer, wherein the sacrificial layer has a flat surface and at least one opening extending therethrough; a wafer layer bonded to the sacrificial layer, wherein the wafer layer has at least one MEMS via; a conductor stack within the at least one MEMS via; a MEMS structure formed in the wafer; and a cavity between the isolation layer and the MEMS structure.
2. The MEMS of claim 1 , further comprising an anchor electrode on the isolation layer and wherein the conductor stack extends to and contacts the anchor electrode.
3. The MEMS of claim 1 , wherein the wafer layer has a thickness between 2 to 100 um.
4. The MEMS of claim 1 , further comprising an opening in the sacrificial layer aligned to at least one MEMS via, the conductor stack extending through the opening.
5. The MEMS of claim 1 , wherein the conductor stack is in the form of a trench surrounding a region of the sacrificial layer, a single via, or multiple vias.
6. The MEMS of claim 1 , wherein the at least one opening comprises about five percent or less of the surface area of the sacrificial layer.
7. A system, comprising: a substrate; an isolation layer atop the substrate; a sacrificial layer atop the isolation layer; a first opening extending through the sacrificial layer; a wafer layer bonded to the sacrificial layer; a second opening extending through the wafer layer, and aligned with the first opening; a conductor stack filling the first opening and the second opening, wherein the conductor stack comprises doped polysilicon; an etch hole extending through the wafer layer; and a cavity under a region of the wafer layer.
8. The system of claim 7 , further including: a MEMS structure formed in the wafer layer.
9. The system of claim 7 , further comprising: a contact atop the conductor stack.
10. The system of claim 9 , wherein the contact atop the conductor stack comprises a material selected from the group consisting of Ti, W, Al, Cu, polysilicon, compositions thereof, and combinations thereof.
11. The system of claim 7 , further comprising an electrode on the isolation layer.
12. The system of claim 11 wherein the electrode on the isolation layer is aligned with the conductor stack.
13. The system of claim 7 , wherein the wafer layer comprises a bulk silicon layer.
14. A system comprising: a silicon-containing substrate; a nitride layer on the substrate; a sacrificial oxide layer on the nitride layer, wherein the sacrificial oxide layer has at least one opening extending therethrough; a silicon layer bonded to the sacrificial layer, wherein the silicon layer has at least one MEMS via extending therethrough, the at least one MEMS via being aligned with the at least one opening in the sacrificial oxide layer; a polysilicon conductor within the at least one MEMS via and the at least one opening in the sacrificial oxide; a MEMS structure formed in the silicon layer; and a cavity between the nitride layer and the MEMS structure.
15. The system of claim 14 , further comprising an electrode on the nitride layer and aligned with the polysilicon conductor.
16. The system of claim 14 , wherein the silicon has a thickness of from about 2 μm to about 100 μm.
17. The system of claim 14 , further comprising a contact atop the polysilicon conductor.
18. The system of claim 14 , wherein the polysilicon extends through the silicon layer and partially overlies the silicon layer.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
July 29, 2013
June 3, 2014
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