Semiconductor integrated circuit apparatus having I/O signal line

1. A semiconductor integrated circuit apparatus comprising: a plurality of column select signal lines extended in parallel to each other with a predetermined distance provided therebetween; an upper segment I/O line arranged in a selected space among spaces formed between the respective column select signal lines; and a local I/O line arranged to overlap the upper segment I/O line, and disposed over the upper segment I/O line, wherein the plurality of column select signal lines, the upper segment I/O line, and the local I/O line are extended in the same direction.

2. The semiconductor integrated circuit apparatus according to claim 1 , further comprising a power mesh line arranged in a space where the upper segment I/O line is not arranged, among the spaces formed between the respective column select signal lines.

3. The semiconductor integrated circuit apparatus according to claim 1 , further comprising a transmission transistor configured to transmit a signal of the upper segment I/O line to the local I/O line.

4. The semiconductor integrated circuit apparatus according to claim 3 , further comprising a lower segment I/O line arranged to cross the column select signal lines, wherein the lower segment I/O line is electrically isolated at intersections with the column select signal lines, and electrically connected to the upper segment I/O line.

5. The semiconductor integrated circuit apparatus according to claim 1 , wherein each of the column select signal lines comprises a pair of unit column select signal lines.

6. A semiconductor integrated circuit apparatus comprising: a lower segment I/O line and a lower segment I/O line bar extended in parallel to a first direction with a predetermined distance provided therebetween; a plurality of column select signal lines arranged to cross the lower segment I/O line and the lower segment I/O line bar and extended in parallel to each other with a predetermined distance provided therebetween, thereby defining first to fourth spaces; an upper segment I/O line arranged in the first space among the spaces corresponding to the distances between the respective column select signal lines; an upper segment I/O line bar arranged in the second space among the spaces corresponding to the distances between the respective column select signal lines; a local I/O line formed in the first space so as to partially overlap the upper segment I/O line; a local I/O line bar formed in the second space so as to partially overlap the upper segment I/O line bar; and power mesh lines arranged in the third and fourth spaces, respectively.

7. The semiconductor integrated circuit apparatus according to claim 6 , further comprising: a first transmission transistor positioned between the lower segment I/O line and the lower segment I/O line bar and configured to transmit a signal of the upper segment I/O line to the local I/O line; and a second transmission transistor positioned between the lower segment I/O line and the lower segment I/O line bar and configured to transmit a signal of the upper segment I/O line bar to the local I/O line bar.

8. The semiconductor integrated circuit apparatus according to claim 6 , wherein the lower segment I/O line is electrically isolated at intersections with the column select signal lines, and electrically connected to the upper segment I/O line.

9. The semiconductor integrated circuit apparatus according to claim 6 , wherein each of the column select signal lines comprises a pair of unit column select signal lines.

10. A semiconductor integrated circuit apparatus comprising: a semiconductor substrate; a lower segment I/O line and a lower segment I/O line bar formed of a first metal layer over the semiconductor substrate and extended in parallel to a first direction with a predetermined distance provided therebetween; a plurality of column select signal lines formed of a second metal layer, arranged to cross the lower segment I/O line and the lower segment I/O line bar, and extended in parallel to each other with a predetermined distance provided therebetween, thereby defining first to fourth spaces; an upper segment I/O line formed of the second metal layer and arranged in the first space among the spaces corresponding to the distances between the respective column select signal lines; an upper segment I/O line bar formed of the second metal layer and arranged in the second space among the spaces corresponding to the distances between the respective column select signal lines; a local I/O line formed of a third metal layer and formed in the first space so as to partially overlap the upper segment I/O line; a local I/O line bar formed of the third metal layer and formed in the second space so as to partially overlap the upper segment I/O line bar; and power mesh lines arranged in the third and fourth spaces, respectively, wherein insulating layers are interposed between the semiconductor substrate and the first metal layer, between the first metal layer and the second metal layer, and between the second metal layer and the third metal layer, respectively.

11. The semiconductor integrated circuit apparatus according to claim 10 , further comprising: a first transmission transistor positioned between the lower segment I/O line and the lower segment I/O line bar and configured to transmit a signal of the upper segment I/O line to the local I/O line; and a second transmission transistor positioned between the lower segment I/O line and the lower segment I/O line bar and configured to transmit a signal of the upper segment I/O line bar to the local I/O line bar.

12. The semiconductor integrated circuit apparatus according to claim 10 , wherein the lower segment I/O line is electrically isolated at intersections with the column select signal lines, and electrically connected to the upper segment I/O line.

13. The semiconductor integrated circuit apparatus according to claim 10 , wherein each of the column select signal lines comprises a pair of unit column select signal lines.