Disclosed herein is a double side cooling power semiconductor module including: a first cooler having a concave part formed in one surface thereof in a thickness direction; a first semiconductor chip mounted on the concave part of the first cooler; a second cooler having one surface and the other surface and formed on one surface of the first cooler so that one surface thereof contacts the first semiconductor chip; a circuit board formed on the other surface of the second cooler; a second semiconductor chip mounted on the circuit board; and a flexible substrate having a circuit layer electrically connecting the first and second semiconductor chips to each other.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A double side cooling power semiconductor module comprising: a first cooler having a concave part formed in one surface thereof in a thickness direction; a first semiconductor chip mounted on the concave part of the first cooler; a second cooler having one surface and the other surface and formed on one surface of the first cooler so that one surface thereof contacts the first semiconductor chip; a circuit board formed on the other surface of the second cooler; a second semiconductor chip mounted on the circuit board; and a flexible substrate having a circuit layer electrically connecting the first and second semiconductor chips to each other.
2. The double side cooling power semiconductor module as set forth in claim 1 , wherein the flexible substrate is adhered to outer peripheral surfaces of the first and second coolers.
3. The double side cooling power semiconductor module as set forth in claim 1 , further comprising: a first insulation layer formed on a bottom surface of the concave part of the first cooler; and a first circuit pattern formed on the first insulation layer, wherein the first semiconductor chip is bonded to the first circuit pattern, the circuit layer of flexible substrate includes a circuit pattern and a via, and the via electrically connects the first circuit pattern and the circuit pattern to each other.
4. The double side cooling power semiconductor module as set forth in claim 3 , wherein the first circuit pattern includes a gate pattern and an emitter pattern.
5. The double side cooling power semiconductor module as set forth in claim 1 , further comprising: a second insulation layer formed on one surface of the second cooler; and a second circuit pattern formed on the second insulation layer, wherein the first semiconductor chip is bonded to the second circuit pattern.
6. The double side cooling power semiconductor module as set forth in claim 5 , wherein the second circuit pattern is a collector pattern.
7. The double side cooling power semiconductor module as set forth in claim 1 , wherein the first semiconductor chip includes an insulated gate bipolar transistor (IGBT) and a diode.
8. The double side cooling power semiconductor module as set forth in claim 7 , further comprising a spacer formed between the insulation gate bipolar transistor (IGBT) and one surface of the second cooler.
9. The double side cooling power semiconductor module as set forth in claim 1 , wherein the second semiconductor chip is a control element.
10. The double side cooling power semiconductor module as set forth in claim 1 , wherein each of the first and second coolers has at least one cooling passage formed at an inner portion thereof in a length direction.
11. A multi-stacked power semiconductor module package comprising: a 1-1th cooler having a first concave part formed in one surface thereof in a thickness direction; a 1-1th semiconductor chip mounted on the first concave part of the 1-1th cooler; a 1-2th cooler formed on one surface of the 1-1th cooler so that one surface thereof is formed with a second concave part in a thickness direction and the other surface thereof contacts the 1-1th semiconductor chip; a 1-2th semiconductor chip mounted on the second concave part of the 1-2th cooler; a second cooler having one surface and the other surface and formed on one surface of the 1-2th cooler so that one surface thereof contacts the 1-2th semiconductor chip; a circuit board formed on the other surface of the second cooler; a second semiconductor ship mounted on the circuit board; a first flexible substrate formed with a circuit layer electrically connecting the 1-1th semiconductor chip and the second semiconductor chip to each other; and a second flexible substrate formed with a circuit layer electrically connecting the 1-2th semiconductor chip and the second semiconductor chip to each other.
12. The multi-stacked power semiconductor module package as set forth in claim 11 , wherein the first flexible substrate is adhered to outer peripheral surfaces of the 1-1th cooler, the 1-2th cooler, and the second cooler.
13. The multi-stacked power semiconductor module package as set forth in claim 11 , wherein the second flexible substrate is adhered to outer peripheral surfaces of the 1-2th cooler and the second cooler.
14. The multi-stacked power semiconductor module package as set forth in claim 11 , further comprising: a 1-1th insulation layer formed on a bottom surface of the first concave part of the 1-1th cooler; a 1-1th circuit pattern formed on the 1-1th insulation layer; a 1-2th insulation layer formed on the other surface of the 1-2th cooler; and a 1-2th circuit pattern formed on the 1-2th insulation layer, wherein one surface of the 1-1th semiconductor chip is bonded to the 1-1th circuit pattern and the other surface thereof is bonded to the 1-2th circuit pattern.
15. The multi-stacked power semiconductor module package as set forth in claim 14 , wherein the 1-1th circuit pattern includes a gate pattern and an emitter pattern, and the 1-2th circuit pattern is a collector pattern.
16. The multi-stacked power semiconductor module package as set forth in claim 11 , further comprising: a 1-3th insulation layer formed on a bottom surface of the second concave part of the 1-2th cooler; a 1-3th circuit pattern formed on the 1-3th insulation layer; a second insulation layer formed on one surface of the second cooler; and a second circuit pattern formed on the second insulation layer, wherein one surface of the 1-2th semiconductor chip is bonded to the 1-3th circuit pattern and the other surface thereof is bonded to the second circuit pattern.
17. The multi-stacked power semiconductor module package as set forth in claim 16 , wherein the 1-3th circuit pattern includes a gate pattern and an emitter pattern, and the second circuit pattern is a collector pattern.
18. The multi-stacked power semiconductor module package as set forth in claim 11 , wherein each of the 1-1th and 1-2th semiconductor chips includes an insulated gate bipolar transistor (IGBT) and a diode.
19. The multi-stacked power semiconductor module package as set forth in claim 11 , wherein the second semiconductor chip is a control element.
20. The multi-stacked power semiconductor module package as set forth in claim 11 , wherein each of the 1-1th cooler, the 1-2th cooler, and the second cooler has at least one cooling passage formed at an inner portion thereof in a length direction.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
June 25, 2012
June 17, 2014
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